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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Datasheet
The Intel(R) LXT9785 and Intel(R) LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide Serial/Source Synchronous Serial Media Independent Interfaces (SMII/SS-SMII) and Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9785 and LXT9785E are identical except for the IP telephony features included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply power if the DTE at the far end requires power over the cable, such as an IP telephone. Each network port can provide a twisted-pair (TP) or Low-Voltage Positive Emitter Coupled Logic (LVPECL) interface. The twisted-pair interface supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair. The LVPECL interface supports 100 Mbps (100BASE-FX) Ethernet over fiber-optic media. The LXT9785/LXT9785E provides three discrete LED driver outputs for each port. The devices support both half-duplex and full-duplex operation at 10 Mbps and 100 Mbps and require only a single 2.5 V power supply.
Applications
Enterprise switches IP telephony switches Storage Area Networks Multi-port Network Interface Cards (NICs)
Product Features
Eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters. 100BASE-FX fiber-optic capability on all ports. 2.5 V operation. Low power consumption; 250 mW per port typical. Multiple RMII or SMII/SS-SMII ports for independent PHY port operation. Auto MDI/MDIX crossover capability. Proprietary Optimal Signal ProcessingTM architecture improves SNR by 3 dB over ideal analog filters. Optimized for dual-high stacked RJ-45 applications. MDIO sectionalization into 2x4 or 1x8 configurations. Supports both auto-negotiation systems and legacy systems without auto-negotiation capability. Robust baseline wander correction. Configurable through the MDIO port or external control pins. JTAG boundary scan. 208-pin PQFP: LXT9785HC, LXT9785EHC, LXT9785HE. 241-ball BGA: LXT9785BC, LXT9785EBC. 196-ball BGA: LXT9785MBC DTE detection for remote powering applications (LXT9785E only). Extended temperature operation of -40oC to +85oC (LXT9785HE).
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) LXT9785 and Intel(R) LXT9785E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2003, Intel Corporation
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
Contents
1.0 Introduction.................................................................................................................................. 18 1.1 1.2 2.0 3.0 What You Will Find in This Document ................................................................................ 18 Related Documents ............................................................................................................ 18
Block Diagram ............................................................................................................................. 19 Pin/Ball Assignments and Signal Descriptions ........................................................................ 20 3.1 PQFP Pin Assignments ...................................................................................................... 20 3.1.1 PQFP Pin Assignments - RMII Configuration ....................................................... 21 3.1.2 PQFP Pin Assignments - SMII Configuration........................................................ 26 3.1.3 PQFP Pin Assignments - SS-SMII Configuration.................................................. 31 PQFP Signal Descriptions .................................................................................................. 36 3.2.1 Signal Name Conventions ..................................................................................... 36 3.2.2 PQFP Signal Descriptions - RMII, SMII, and SS-SMII Configurations.................. 36 BGA23 Ball Assignments.................................................................................................... 51 3.3.1 RMII BGA23 Ball List ............................................................................................. 52 3.3.2 SMII BGA23 Ball List ............................................................................................. 62 3.3.3 SS-SMII BGA23 Ball List ....................................................................................... 72 BGA23 Signal Descriptions ................................................................................................ 82 3.4.1 Signal Name Conventions ..................................................................................... 82 3.4.2 Signal Descriptions - RMII, SMII, and SS-SMII Configurations............................. 82 BGA15 Ball Assignments.................................................................................................... 98 3.5.1 BGA15 Ball List...................................................................................................... 99 BGA15 Signal Descriptions ..............................................................................................109 3.6.1 Signal Name Conventions ...................................................................................109 3.6.2 Signal Descriptions - SMII and SS-SMII Configurations .....................................109 Introduction .......................................................................................................................116 4.1.1 OSPTM Architecture .............................................................................................116 4.1.2 Comprehensive Functionality ..............................................................................117 4.1.2.1 Sectionalization ....................................................................................117 Interface Descriptions .......................................................................................................117 4.2.1 10/100 Network Interface.....................................................................................117 4.2.1.1 Twisted-Pair Interface ..........................................................................118 4.2.1.2 MDI Crossover (MDIX).........................................................................119 4.2.1.3 Fiber Interface......................................................................................119 Media Independent Interface (MII) Interfaces...................................................................119 4.3.1 Global MII Mode Select .......................................................................................119 4.3.2 Internal Loopback ................................................................................................120 4.3.3 RMII Data Interface..............................................................................................120 4.3.4 Serial Media Independent Interface (SMII) and Source SynchronousSerial Media Independent Interface (SS-SMII) ....................................................121 4.3.4.1 SMII Interface.......................................................................................121 4.3.4.2 Source Synchronous-Serial Media Independent Interface ..................121 4.3.5 Configuration Management Interface ..................................................................121 4.3.6 MII Isolate ............................................................................................................121
3.2 3.3
3.4 3.5 3.6
4.0
Functional Description..............................................................................................................116 4.1
4.2
4.3
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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Contents
4.4
4.5
4.6
4.7
4.8
4.9
4.3.7 MDIO Management Interface .............................................................................. 121 4.3.8 MII Sectionalization.............................................................................................. 123 4.3.9 MII Interrupts........................................................................................................ 123 4.3.10 Global Hardware Control Interface ...................................................................... 124 4.3.11 FIFO Initial Fill Values.......................................................................................... 124 Operating Requirements................................................................................................... 125 4.4.1 Power Requirements ........................................................................................... 125 4.4.2 Clock/SYNC Requirements ................................................................................. 125 4.4.2.1 Reference Clock .................................................................................. 125 4.4.2.2 TxCLK Signal (SS-SMII only)............................................................... 125 4.4.2.3 TxSYNC Signal (SMII/SS-SMII)........................................................... 125 4.4.2.4 RxSYNC Signal (SS-SMII only) ........................................................... 125 4.4.2.5 RxCLK Signal (SS-SMII only) .............................................................. 126 Initialization ....................................................................................................................... 126 4.5.1 MDIO Control Mode............................................................................................. 126 4.5.2 Hardware Control Mode....................................................................................... 126 4.5.3 Power-Down Mode .............................................................................................. 127 4.5.3.1 Global (Hardware) Power Down .......................................................... 128 4.5.3.2 Port (Software) Power Down ............................................................... 128 4.5.4 Reset ................................................................................................................... 128 4.5.5 Hardware Configuration Settings......................................................................... 129 Link Establishment............................................................................................................ 129 4.6.1 Auto-Negotiation .................................................................................................. 129 4.6.1.1 Base Page Exchange .......................................................................... 129 4.6.1.2 Manual Next Page Exchange .............................................................. 130 4.6.1.3 Controlling Auto-Negotiation ................................................................ 130 4.6.1.4 Link Criteria.......................................................................................... 130 4.6.1.5 Parallel Detection................................................................................. 131 4.6.1.6 Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode .......................................................... 131 Serial MII Operation.......................................................................................................... 132 4.7.1 SMII Reference Clock.......................................................................................... 135 4.7.2 TxSYNC Pulse (SMII/SS-SMII)............................................................................ 135 4.7.3 Transmit Data Stream.......................................................................................... 135 4.7.3.1 Transmit Enable................................................................................... 135 4.7.3.2 Transmit Error ...................................................................................... 135 4.7.4 Receive Data Stream........................................................................................... 136 4.7.4.1 Carrier Sense....................................................................................... 136 4.7.4.2 Receive Data Valid .............................................................................. 136 4.7.4.3 Receive Error ....................................................................................... 136 4.7.4.4 Receive Status Encoding..................................................................... 136 4.7.5 Collision ............................................................................................................... 136 4.7.6 Source Synchronous-Serial Media Independent Interface .................................. 137 RMII Operation ................................................................................................................. 141 4.8.1 RMII Reference Clock.......................................................................................... 141 4.8.2 Transmit Enable................................................................................................... 142 4.8.3 Carrier Sense & Data Valid.................................................................................. 142 4.8.4 Receive Error....................................................................................................... 142 4.8.5 Out-of-Band Signaling ......................................................................................... 142 4.8.6 4B/5B Coding Operations .................................................................................... 142 100 Mbps Operation ......................................................................................................... 145
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
4.9.1 4.9.2
4.10
4.11
4.12
4.13
4.14
100BASE-X Network Operations .........................................................................145 100BASE-X Protocol Sublayer Operations..........................................................145 4.9.2.1 PCS Sublayer ......................................................................................145 4.9.3 PMA Sublayer ......................................................................................................147 4.9.3.1 Link ......................................................................................................148 4.9.3.2 Link Failure Override............................................................................148 4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................148 4.9.3.4 Carrier Sense (SMII) ............................................................................148 4.9.3.5 Receive Data Valid (SMII)....................................................................148 4.9.3.6 Twisted-Pair PMD Sublayer .................................................................149 4.9.3.7 Fiber PMD Sublayer.............................................................................149 10 Mbps Operation ...........................................................................................................150 4.10.1 Preamble Handling ..............................................................................................150 4.10.2 Dribble Bits ..........................................................................................................151 4.10.3 Link Test ..............................................................................................................151 4.10.3.1 Link Failure ..........................................................................................151 4.10.4 Jabber ..................................................................................................................151 DTE Discovery Process ....................................................................................................152 4.11.1 Definitions ............................................................................................................152 4.11.2 Interaction between Processor, MAC, and PHY ..................................................153 4.11.3 Management Interface and Control .....................................................................153 4.11.4 DTE Discovery Process Flow ..............................................................................154 4.11.5 DTE Discovery Behavior......................................................................................155 Monitoring Operations ......................................................................................................157 4.12.1 Monitoring Auto-Negotiation ................................................................................157 4.12.2 Per-Port LED Driver Functions ............................................................................157 4.12.3 Out-of-Band Signaling .........................................................................................158 4.12.4 Boundary Scan Interface .....................................................................................159 4.12.5 State Machine ......................................................................................................159 4.12.6 Instruction Register ..............................................................................................159 4.12.7 Boundary Scan Register ......................................................................................159 Cable Diagnostics Overview .............................................................................................160 4.13.1 Features...............................................................................................................160 4.13.2 Operation .............................................................................................................160 4.13.2.1 Short and Long Cable Testing Requirements ......................................160 4.13.2.2 Precision ..............................................................................................160 4.13.3 Implementation Considerations ...........................................................................161 4.13.4 Basic Implementation ..........................................................................................161 Link Hold-Off Overview .....................................................................................................162 4.14.1 Features...............................................................................................................162 4.14.2 Operation .............................................................................................................163 Design Recommendations................................................................................................164 General Design Guidelines ...............................................................................................164 5.2.1 Power Supply Filtering .........................................................................................164 5.2.2 Power and Ground Plane Layout Considerations................................................165 5.2.2.1 Chassis Ground ...................................................................................165 5.2.3 MII Terminations ..................................................................................................165 5.2.4 Twisted-Pair Interface ..........................................................................................165 5.2.4.1 Magnetic Requirements .......................................................................166
5.0
Application Information ............................................................................................................164 5.1 5.2
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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Contents
5.3 6.0 7.0 8.0 9.0
5.2.5 The Fiber Interface .............................................................................................. 166 5.2.6 LED Circuit........................................................................................................... 167 Typical Application Circuits............................................................................................... 168
Test Specifications.................................................................................................................... 173 Register Definitions................................................................................................................... 199 Package Specifications............................................................................................................. 221 Ordering Information................................................................................................................. 227
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Intel(R) LXT9785/LXT9785E Block Diagram ................................................................................. 19 Intel(R) LXT9785 and Intel(R) LXT9785E RMII 208-Pin PQFP Assignments .................................. 21 Intel(R) LXT9785/LXT9785E SMII 208-Pin PQFP Assignments ................................................... 26 Intel(R) LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments ............................................. 31 Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)...................................... 51 Intel(R) LXT9785MBC 196-Ball BGA15 Assignments (Top View) ................................................ 98 Intel(R) LXT9785/LXT9785E Interfaces ...................................................................................... 118 Intel(R) LXT9785/LXT9785E Internal Loopback.......................................................................... 120 Intel(R) LXT9785/LXT9785E Management Interface Read Frame Structure.............................. 122 Intel(R) LXT9785/LXT9785E Management Interface Write Frame Structure .............................. 122 Intel(R) LXT9785/LXT9785E Port Address Scheme ................................................................... 123 Intel(R) LXT9785/LXT9785E Interrupt Logic ............................................................................... 124 Intel(R) LXT9785/LXT9785E Initialization Sequence .................................................................. 127 Intel(R) LXT9785/LXT9785E Auto-Negotiation Operation........................................................... 131 Intel(R) LXT9785/LXT9785E Typical SMII Interface Diagram ..................................................... 133 Intel(R) LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram ................................ 134 Intel(R) LXT9785/LXT9785E 100 Mbps Serial MII Data Flow ..................................................... 135 Intel(R) LXT9785/LXT9785E Serial MII Transmit Synchronization ............................................. 136 Intel(R) LXT9785/LXT9785E Serial MII Receive Synchronization .............................................. 137 Intel(R) LXT9785/LXT9785E Typical SS-SMII Interface Diagram ............................................... 139 Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram .......................... 140 Intel(R) LXT9785/LXT9785E SS-SMII Transmit Timing .............................................................. 141 Intel(R) LXT9785/LXT9785E SS-SMII Receive Timing ............................................................... 141 Intel(R) LXT9785/LXT9785E RMII Data Flow ............................................................................. 142 Intel(R) LXT9785/LXT9785E Typical RMII Interface Diagram..................................................... 143 Intel(R) LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram................................ 144 Intel(R) LXT9785/LXT9785E 100BASE-X Frame Format ........................................................... 145 Intel(R) LXT9785/LXT9785E Protocol Sublayers ........................................................................ 146 Typical IP Telephone System Connection................................................................................ 152 Intel(R) LXT9785E Negotiation Flow Chart ................................................................................. 156 Intel(R) LXT9785/LXT9785E LED Pulse Stretching .................................................................... 158 Intel(R) LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling.................................. 158 LED Circuit ............................................................................................................................... 167 Intel(R) LXT9785/LXT9785E Power and Ground Supply Connections ....................................... 168 Intel(R) LXT9785/LXT9785E Typical Twisted-Pair Interface ....................................................... 169 Recommended Intel(R) LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry ...... 170 Recommended Intel(R) LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ......... 171 ON Semiconductor Triple PECL-to-LVPECL Translator .......................................................... 172
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing.............................................178 Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing............................................179 Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing.............................................180 Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing............................................181 Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Receive Timing .................................................182 Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing ................................................183 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing.......................................184 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing......................................185 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing.......................................186 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing......................................187 Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing ...........................................188 Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing ..........................................189 Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing ............................................190 Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing ...........................................191 Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing ............................................192 Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing ...........................................193 Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Receive Timing.................................................194 Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing................................................195 Intel(R) LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing ...............................196 Intel(R) LXT9785/LXT9785E Fast Link Pulse Timing ..................................................................196 Intel(R) LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC)...............................197 Intel(R) LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY) ...............................197 Intel(R) LXT9785/LXT9785E Power-Up Timing...........................................................................198 Intel(R) LXT9785/LXT9785E Reset Recovery Timing .................................................................198 PHY Identifier Bit Mapping........................................................................................................203 Intel(R) LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification ...............................221 Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Top/Side View (LXT9785BC) .222 Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View (LXT9785BC) ....223 Intel(R) LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC) ........225 Ordering Information - Sample .................................................................................................228
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Intel(R) LXT9785/LXT9785E Signal Type Descriptions.................................................................20 Intel(R) LXT9785/LXT9785E RMII PQFP Pin List ......................................................................... 22 Intel(R) LXT9785/LXT9785E SMII PQFP Pin List ......................................................................... 27 Intel(R) LXT9785/LXT9785 SS-SMII PQFP Pin List...................................................................... 32 Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP ................................................... 36 Intel(R) LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions - PQFP ................... 39 Intel(R) LXT9785/LXT9785E SMII Specific Signal Descriptions - PQFP...................................... 39 Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - PQFP................................ 40 Intel(R) LXT9785/LXT9785E MDIO Control Interface Signals - PQFP......................................... 41 Intel(R) LXT9785/LXT9785E Signal Detect - PQFP ..................................................................... 42 Intel(R) LXT9785/LXT9785E Network Interface Signal Descriptions - PQFP............................... 42 Intel(R) LXT9785/LXT9785E JTAG Test Signal Descriptions - PQFP.......................................... 43 Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP .................................... 43 Intel(R) LXT9785/LXT9785E LED Signal Descriptions - PQFP....................................................47 Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - PQFP..................................... 48 Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - PQFP...................................................... 50 Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations............................................... 50
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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Contents
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name ...... 52 Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location ...... 57 Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name....... 62 Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location....... 67 Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name. 72 Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location. 77 Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - BGA23 ................................................. 82 Intel(R) LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions - BGA23 ................. 85 Intel(R) LXT9785/LXT9785E SMII Specific Signal Descriptions - BGA23 .................................... 85 Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - BGA23 .............................. 86 Intel(R) LXT9785/LXT9785E MDIO Control Interface Signals - BGA23 ....................................... 87 Intel(R) LXT9785/LXT9785E Signal Detect - BGA23 ................................................................... 88 Intel(R) LXT9785/LXT9785E Network Interface Signal Descriptions - BGA23............................. 88 Intel(R) LXT9785/LXT9785E JTAG Test Signal Descriptions - BGA23........................................ 89 Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23 .................................. 90 Intel(R) LXT9785/LXT9785E LED Signal Descriptions - BGA23 .................................................. 94 Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - BGA23................................... 95 Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - BGA23 .................................................... 97 Intel(R) LXT9785/LXT9785E Receive FIFO Depth Configurations ............................................... 97 Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name ......................... 99 Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/SS-SMII) ......................................................................................................................... 103 Intel(R) LXT9785 BGA15 Signal Descriptions ............................................................................ 109 Intel(R) LXT9785/LXT9785E MDIX Selection ............................................................................. 119 Intel(R) LXT9785/LXT9785E MII Mode Select ............................................................................ 120 Intel(R) LXT9785/9785E Global Hardware Configuration Settings ............................................. 129 Intel(R) LXT9785/LXT9785E SMII Signal Summary ................................................................... 132 Intel(R) LXT9785/LXT9785E RX Status Encoding Bit Definitions ............................................... 137 Intel(R) LXT9785/LXT9785E SS-SMII ......................................................................................... 138 4B/5B Coding ........................................................................................................................... 147 Next Page Message #5 Code Word Definitions ....................................................................... 155 BSR Mode of Operation ........................................................................................................... 159 Supported JTAG Instructions ................................................................................................... 159 Intel(R) LXT9785/LXT9785E Magnetics Requirements .............................................................. 166 Intel(R) LXT9785/LXT9785E Absolute Maximum Ratings .......................................................... 173 Intel(R) LXT9785/LXT9785E Operating Conditions .................................................................... 173 Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%) . 174 Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) . 175 Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics - SD Pins ....................... 175 Intel(R) LXT9785/LXT9785E Required Clock Characteristics ..................................................... 175 Intel(R) LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics .................................... 176 Intel(R) LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics .................................... 176 Intel(R) LXT9785/LXT9785E 10BASE-T Transceiver Characteristics......................................... 177 Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters ......................... 178 Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters ........................ 179 Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters ......................... 180 Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters ........................ 181 Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters ............................. 182 Intel(R) LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters .............................. 183 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters ................... 184
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103
Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing......................................185 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters ...................186 Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters ..................187 Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters .......................188 Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters ......................189 Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters.........................190 Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters........................191 Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters.........................192 Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters........................193 Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters .............................194 Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters ............................195 Intel(R) LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters............196 Intel(R) LXT9785/LXT9785E MDIO Timing Parameters..............................................................197 Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters .......................................................198 Intel(R) LXT9785/LXT9785E Reset Recovery Timing Parameters .............................................198 Intel(R) LXT9785/LXT9785E Register Set...................................................................................199 Control Register (Address 0) ....................................................................................................200 Status Register (Address 1)......................................................................................................201 PHY Identification Register 1 (Address 2) ................................................................................203 PHY Identification Register 2 (Address 3) ................................................................................203 Auto-Negotiation Advertisement Register (Address 4) .............................................................204 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) ...................................205 Auto-Negotiation Expansion Register (Address 6) ...................................................................206 Auto-Negotiation Next Page Transmit Register (Address 7) ....................................................206 Auto-Negotiation Link Partner Next Page Receive Register (Address 8).................................207 Port Configuration Register (Address 16, Hex 10) ...................................................................207 Quick Status Register (Address 17, Hex 11) ............................................................................209 Interrupt Enable Register (Address 18, Hex 12).......................................................................211 Interrupt Status Register (Address 19, Hex 13)........................................................................212 LED Configuration Register (Address 20, Hex 14) ...................................................................213 Receive Error Count Register (Address 21, Hex 15)................................................................214 RMII Out-of-Band Signaling Register (Address 25, Hex 19) ....................................................215 Trim Enable Register (Address 27, Hex 1B).............................................................................216 Cable Diagnostics Register (Address 29, Hex 1D)...................................................................217 Intel(R) LXT9785/LXT9785E Register Bit Map............................................................................219 Intel(R) LXT9785MBC 196-Ball BGA15 Package Dimensions ...................................................226 Product Information ..................................................................................................................227
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
9
Contents
Revision History
Revision Number: 007 Revision Date: August 28, 2003 Page 21 22 26 27 31 32 36 40 43 50 51 52 57 62 67 72 77 82 86 90 97 98 116 117 119 119 120 Description Modified Figure 2 "Intel(R) LXT9785 and Intel(R) LXT9785E RMII 208-Pin PQFP Assignments". Modified Table 2 "Intel(R) LXT9785/LXT9785E RMII PQFP Pin List". Modified Figure 3 "Intel(R) LXT9785/LXT9785E SMII 208-Pin PQFP Assignments". Modified Table 3 "Intel(R) LXT9785/LXT9785E SMII PQFP Pin List". Modified Figure 4 "Intel(R) LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments". Modified Table 4 "Intel(R) LXT9785/LXT9785 SS-SMII PQFP Pin List". Modified Table 5 "Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP". Modified Table 8 "Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - PQFP". Modified Table 13 "Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP". Modified Table 16 "Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - PQFP". Replaced old Figures 5, 6, and 7 with Figure 5 "Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)". Modified Table 18 "Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name". Modified Table 19 "Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location". Modified Table 20 "Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name". Modified Table 21 "Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location" Modified Table 22 "Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name". Modified Table 23 "Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location". Modified Table 23 "Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location". Modified Table 27 "Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - BGA23". Modified Table 32 "Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23". Modified Table 35 "Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - BGA23". Added Section 3.5, "BGA15 Ball Assignments" (including Figure 6 "Intel(R) LXT9785MBC 196-Ball BGA15 Assignments (Top View)", Table 37 "Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name" through Table 39 "Intel(R) LXT9785 BGA15 Signal Descriptions". Added second paragraph under Section 4.1, "Introduction". Added note under Section 4.1.2.1, "Sectionalization". Added note under Table 40 "Intel(R) LXT9785/LXT9785E MDIX Selection". Added note under Section 4.3, "Media Independent Interface (MII) Interfaces". Added note to Table 41 "Intel(R) LXT9785/LXT9785E MII Mode Select".
10
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
Revision Number: 007 Revision Date: August 28, 2003 Page 120 121 121 123 124 125 127 128 128 129 130 130 131 131 136 141 148 148 149 149 149 150 151 152 153 154 155 157 158 160 161 Description Modified/added text under Section 4.3.2, "Internal Loopback". Modified text under Section 4.3.6, "MII Isolate". Section 4.3.7, "MDIO Management Interface": Added note under second paragraph. Added last paragraph. Added note under Section 4.3.8, "MII Sectionalization". Added new Section 4.3.11, "FIFO Initial Fill Values" Modified paragraph three under Section 4.4.1, "Power Requirements". Added notes under second and last paragraphs under Section 4.5.3, "Power-Down Mode". Modified last bullet under Section 4.5.3.1, "Global (Hardware) Power Down". Added last paragraph to Section 4.5.4, "Reset". Modified Table 42 "Intel(R) LXT9785/9785E Global Hardware Configuration Settings". Change heading and modified last line under Section 4.6.1.2, "Manual Next Page Exchange". Section 4.6.1.4, "Link Criteria": Changed scrambler to descrambler in first line. Modified second paragraph. Added two new paragraphs. Added second paragraph under Section 4.6.1.5, "Parallel Detection". Modified paragraphs under Section 4.6.1.6, "Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode". Changed "1110" to "0101" under Section 4.7.4.3, "Receive Error". Added note under first paragraph of Section 4.8, "RMII Operation" Changed "asynchronously" to "synchronously" in second paragraph under Section 4.9.3.3, "Carrier Sense/Data Valid (RMII)". Modified last sentence in first paragraph under Section 4.9.3.4, "Carrier Sense (SMII)". Modified paragraph under Section 4.9.3.6.3, "Polarity Correction". Added note under Section 4.9.3.7, "Fiber PMD Sublayer". Added second paragraph under Section 4.9.3.7.1, "Far End Fault Indications". Modified/added text under Section 4.10.1, "Preamble Handling". Modified text under Section 4.10.4, "Jabber". Modified first paragraph under Section 4.11, "DTE Discovery Process". Modified Item 1 of Section 4.11.2, "Interaction between Processor, MAC, and PHY". Modified second paragraph under Section 4.11.4, "DTE Discovery Process Flow". Added Section 4.11.5, "DTE Discovery Behavior" Added BGA15 information into first paragraph under Section 4.12.2, "Per-Port LED Driver Functions". Added last sentence to first paragraph and note under first paragraph under Section 4.12.3, "Out-ofBand Signaling". Added Section 4.13, "Cable Diagnostics Overview". Modified/added text under Section 4.13.3, "Implementation Considerations".
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
11
Contents
Revision Number: 007 Revision Date: August 28, 2003 Page 162 173 176 178195 178 184 190 198 199 199 200 201 203 203 204 205 206 206 206 207 209 211 212 213 214 215 216 217 219 226 227 Description Added Section 4.14, "Link Hold-Off Overview". Modified Table 52 "Intel(R) LXT9785/LXT9785E Operating Conditions" Modified Table 58 "Intel(R) LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics" Added note to Table 60 "Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters" through Table 77 "Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters". Added table note to Table 60 "Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters". Added table note to Table 66 "Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters". Added table note to Table 72 "Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters" Added software power-down and note to Table 80 "Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters". Modified paragraphs and added last paragraph under Section 7.0, "Register Definitions". Modified Table 82 "Intel(R) LXT9785/LXT9785E Register Set". Modified Table 83 "Control Register (Address 0)". Modified Table 84 "Status Register (Address 1)". Modified Table 85 "PHY Identification Register 1 (Address 2)". Modified Table 86 "PHY Identification Register 2 (Address 3)" Modified Table 87 "Auto-Negotiation Advertisement Register (Address 4)" Modified Table 88 "Auto-Negotiation Link Partner Base Page Ability Register (Address 5)". Modified Table 89 "Auto-Negotiation Expansion Register (Address 6)". Modified Table 90 "Auto-Negotiation Next Page Transmit Register (Address 7)". Modified Table 91 "Auto-Negotiation Link Partner Next Page Receive Register (Address 8)". Modified Table 92 "Port Configuration Register (Address 16, Hex 10)". (Register bits 16.6, 16.4:3) Modified Table 93 "Quick Status Register (Address 17, Hex 11)". (Register bit 17.8) Modified Table 94 "Interrupt Enable Register (Address 18, Hex 12)" Modified Table 95 "Interrupt Status Register (Address 19, Hex 13)" Modified Table 96 "LED Configuration Register (Address 20, Hex 14)" Modified Table 97 "Receive Error Count Register (Address 21, Hex 15)". Modified Table 98 "RMII Out-of-Band Signaling Register (Address 25, Hex 19)". Modified Table 99 "Trim Enable Register (Address 27, Hex 1B)". (Register bit 27.6) Added Table 100 "Cable Diagnostics Register (Address 29, Hex 1D)". Modified Table 101 "Intel(R) LXT9785/LXT9785E Register Bit Map". Added Figure 102 "Intel(R) LXT9785MBC 196-Ball BGA15 Package Dimensions" Modified table and figure under Section 9.0, "Ordering Information".
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
Revision Number: 006 (INTERNAL RELEASE) Revision Date: June 10, 2003 Page 1 36 42 42 43 116 119 120 130 131 136 145 146 148 148 149 149 150 151 152 153 158 166 170 171 173 174 175 175 176 Description Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the second paragraph, front page. Modified Table 5 "Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP". Added last sentence to RXER0 through RXER7 signal description. Modified Table 10 "Intel(R) LXT9785/LXT9785E Signal Detect - PQFP". Modified Table 11 "Intel(R) LXT9785/LXT9785E Network Interface Signal Descriptions - PQFP", Modified Table 13 "Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP". Added note to PREASEL signal description. Modified Section 4.1, "Introduction". Changed "Pseudo-ECL (PECL)" to "Low Voltage PECL (LVPECL)" in the first paragraph, second sentence. Replace text under Section 4.2.1.3, "Fiber Interface". Modified Section 4.3.2, "Internal Loopback". Modified last sentence under Section 4.6.1.4, "Link Criteria". Modified text under Section 4.6.1.5, "Parallel Detection". Added second paragraph. Modified text under Section 4.7.4.3, "Receive Error". Changed "PECL" to "LVPECL in third paragraph, first sentence under Section 4.9.1, "100BASE-X Network Operations". Modified Figure 28 "Intel(R) LXT9785/LXT9785E Protocol Sublayers". Modified Section 4.9.3.3, "Carrier Sense/Data Valid (RMII)". Changed "asynchronously to "synchronously." Modified text under Section 4.9.3.4, "Carrier Sense (SMII)". Revised last sentence in first paragraph. Modified paragraph under Section 4.9.3.6.3, "Polarity Correction". Replaced text under Section 4.9.3.7, "Fiber PMD Sublayer". Modified Section 4.10.1, "Preamble Handling". Added text to last paragraph. Modified first sentence under Section 4.10.4, "Jabber". Modified first paragraph of Section 4.11, "DTE Discovery Process". Modified Item 1 of Section 4.11.2, "Interaction between Processor, MAC, and PHY". Modified Section 4.12.3, "Out-of-Band Signaling". Added sentence to end of first paragraph. Replaced text under Section 5.2.5, "The Fiber Interface". Replaced Figure 36 "Recommended Intel(R) LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry". Replaced Figure 37 "Recommended Intel(R) LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry". Modified Table 52 "Intel(R) LXT9785/LXT9785E Operating Conditions". Modified Table 53 "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)". Modified Table 54 "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)". Added Table 55 "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics - SD Pins". Modified Table 58 "Intel(R) LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics".
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
13
Contents
Revision Number: 006 (INTERNAL RELEASE) Revision Date: June 10, 2003 Page 200 201 204 205 207 207 209 211 212 214 215 216 227 Description Modified Table 83 "Control Register (Address 0)". Modified Table 84 "Status Register (Address 1)". Modified Table 87 "Auto-Negotiation Advertisement Register (Address 4)". Modified Table 88 "Auto-Negotiation Link Partner Base Page Ability Register (Address 5)". Modified Table 91 "Auto-Negotiation Link Partner Next Page Receive Register (Address 8)". Modified Table 92 "Port Configuration Register (Address 16, Hex 10)". Modified Table 93 "Quick Status Register (Address 17, Hex 11)". Modified Table 94 "Interrupt Enable Register (Address 18, Hex 12)" Modified Table 95 "Interrupt Status Register (Address 19, Hex 13)". Changed all references of RO/ SC to R/LH. Modified Table 97 "Receive Error Count Register (Address 21, Hex 15)". Modified Table 98 "RMII Out-of-Band Signaling Register (Address 25, Hex 19)". Added note to Register bit 25.0. Modified Table 99 "Trim Enable Register (Address 27, Hex 1B)". Modified Table 103 "Product Information".
Revision Number: 005 Revision Date: January 2002 Page 1 49 70 109 110 111 112 112 114 129 131 133 Description Added bullet to Product Features Modified Table 12 "Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions" (Added FIFOSEL1 and FIFOSEL0) Added Section 2.6.1.6, "Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode" Modified Figure 38 "Recommended Intel(R) LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry" Added Figure 39 "Recommended Intel(R) LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry" Added Figure 40 "ON Semiconductor Triple PECL-to-LVPECL Translator" Modified Table 28 "Absolute Maximum Ratings" Modified Table 29 "Operating Conditions" Modified Table 31 "Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)"(Output low voltage SD pins - Max) Modified Figure 53 "RMII - 100BASE-TX Receive Timing" and Table 49 "RMII - 100BASE-TX Receive Timing Parameters" Modified Figure 55 "RMII - 100BASE-FX Receive Timing" and Table 51 "RMII - 100BASE-FX Receive Timing Parameters" Modified Figure 57 "RMII - 10BASE-T Receive Timing" and Table 53 "RMII - 10BASE-T Receive Timing Parameters"
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Contents
Revision Number: 005 Revision Date: January 2002 Page 146 148 168 Description Modified Table 69 "Port Configuration Register (Address 16, Hex 10)" (Bits 16.5 and 16.6) Modified Table 71 "Interrupt Enable Register (Address 18, Hex 12)" Added product ordering table and diagram.
Revision Number: 003 Revision Date: April 2001 Page 1 61 85 93 97 97 99 102 122 126 128 128 131 133 140 141 Description Modified and added new language to front page. Reset: Modified language in first paragraph. Added new section on DTE discovery. Supported JTAG Instructions table: replaced long hit streams with hex. LED Circuit: Modified paragraph language. LED Circuit diagram: Modified diagram. Replaced Typical Fiber Interface diagram. Required Clock Characteristics table: Replaced SMII Input frequency and RMII Input frequency symbol with "f". Auto-Negotiation and Fast Link Pulse Timing Parameters: FLP burst width under Typ = 2. Control Register table: Modified table and table notes. PHY Identification Register 2 (Address 3): Modified table. PHY Identifier Bit Mapping: Modified diagram. Auto-Negotiation Expansion: Modified table and table notes. Port Configuration Register table: Modified table and table notes. Trim Enable Register: Modified table (DTE Discovery). Modified Register Bit Map table.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
15
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
1.0
Introduction
This document contains information on the Intel(R) LXT9785/LXT9785E Advanced 8-port 10/100 Mbps Fast Ethernet transceivers.
1.1
What You Will Find in This Document
This document contains the following sections:
* Section 3.0, "Pin/Ball Assignments and Signal Descriptions" on page 20
-- Section 3.1, "PQFP Pin Assignments" on page 20 -- Section 3.2, "PQFP Signal Descriptions" on page 36 -- Section 3.3, "BGA23 Ball Assignments" on page 51 -- Section 3.4, "BGA23 Signal Descriptions" on page 82 -- Section 3.5, "BGA15 Ball Assignments" on page 98 -- Section 3.6, "BGA15 Signal Descriptions" on page 109
This section contains pin/ball assignments and signal descriptions for the following:
* * * * * *
Section 4.0, "Functional Description" on page 116 Section 5.0, "Application Information" on page 164 Section 6.0, "Test Specifications" on page 173 Section 7.0, "Register Definitions" on page 199 Section 8.0, "Package Specifications" on page 221 Section 9.0, "Ordering Information" on page 227
1.2
Related Documents
Document Number 249509 249357 250781 249611
Document Intel(R) LXT9785/LXT9785E Design and Layout Guide Intel LXT9785/LXT9785E Specification Update Intel(R) LXT9785/LXT9785E 100BASE-FX Fiber Optic Transceivers: Connecting a PECL/ LVPECL Interface IP Telephony and DTE Discovery Using Intel Ethernet(R) PHYs
(R)
18
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
2.0
Block Diagram
Figure 1 provides the LXT9785/LXT9785E block diagram.
Figure 1. Intel(R) LXT9785/LXT9785E Block Diagram
RMII/SMII Contr ADD_<4:0> MDIO MDC MDINT
2 2 2
8-Port Global Functions
Management / Mode Select Logic & LED Drivers
Register Set
RESET PWRDN Clock Generator Manchester Encoder REFCLK SYNC (SMII only)
TX PCS
10 100
TxDatan
Parallel/Serial Converter
Scrambler & Encoder
Auto Negotiation
Pulse Shaper
TP Driver
+ + Fiber select n
+
Mgmt Counters
Register Set
ECL Driver
TP / Fiber Out
TPFOPn TPFONn
Clock Generator
LEDn_<2:0>
3
Port LED Drivers
Serial to Parallel Converter Carrier Sense Data Valid Error Detect 10 100 Manchester Decoder Decoder & Descrambler
Media Select
Adaptive EQ with BL Wander Cancellation
100TX +
RX PCS
Slicer
100FX + 10BT
TP / Fiber In
TPFIPn TPFINn
RxDatan
Per-Port Functions
PORT 0
-
PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
19
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.0
3.1
Pin/Ball Assignments and Signal Descriptions
PQFP Pin Assignments
The following sections show PQFP pin assignments and signal descriptions:
* Section 3.1.1, "PQFP Pin Assignments - RMII Configuration" on page 21 * Section 3.1.2, "PQFP Pin Assignments - SMII Configuration" on page 26 * Section 3.1.3, "PQFP Pin Assignments - SS-SMII Configuration" on page 31
Table 1 lists the acronyms and descriptions for signal types. Table 1. Intel(R) LXT9785/LXT9785E Signal Type Descriptions
Acronym Description
AI AO I O OD ST TS SL IP ID
Analog Input Analog Output Input Output Open Drain Output Schmitt Triggered Input Three-State-able Output Slew-rate Limited Output Weak Internal Pull-Up Weak Internal Pull-Down
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.1
PQFP Pin Assignments - RMII Configuration
Figure 2 and Table 2, "Intel(R) LXT9785/LXT9785E RMII PQFP Pin List" on page 22 provide LXT9785/LXT9785 RMII PQFP pin assignments.
Figure 2. Intel(R) LXT9785 and Intel(R) LXT9785E RMII 208-Pin PQFP Assignments
CRS_DV6.......1 RxER6/LINKHOLD..2 TxEN6.......3 TxData6_0.......4 TxData6_1.......5 REFCLK1.......6 RxData5_1.......7 RxData5_0.......8 GNDIO.......9 CRS_DV5.......10 RxER5/FIFOSEL1.....11 TxEN5.......12 TxData5_0.......13 TxData5_1.......14 RxData4_1.......15 RxData4_0.......16 CRS_DV4.......17 VCCIO.......18 GNDIO.......19 RxER4/FIFOSEL0.....20 TxEN4.......21 TxData4_0.......22 TxData4_1.......23 MDC1.......24 MDIO1.......25 MDINT1.......26 RxData3_1.......27 RxData3_0.......28 VCCIO.......29 GNDIO.......30 CRS_DV3.......31 RxER3.......32 TxEN3.......33 TxData3_0.......34 TxData3_1.......35 RxData2_1.......36 RxData2_0.......37 GNDIO.......38 CRS_DV2.......39 RxER2/PREASEL .....40 TxEN2.......41 TxData2_0.......42 TxData2_1.......43 REFCLK0.......44 RxData1_1.......45 RxData1_0.......46 VCCIO.......47 GNDIO.......48 CRS_DV1.......49 RxER1/PAUSE.......50 TxEN1.......51 TxData1_0.......52
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
TxData1_1 ...... 53 RxData0_1 ...... 54 RxData0_0 ...... 55 VCCIO ...... 56 GNDIO ...... 57 CRS_DV0 ...... 58 RxER0/MDIX ...... 59 TxEN0 ...... 60 TxData0_0 ...... 61 TxData0_1 ...... 62 MDC0 ...... 63 MDIO0 ...... 64 VCCD ...... 65 GNDD ...... 66 MDINT0 ...... 67 LED3_3 ...... 68 LED3_2 ...... 69 LED3_1 ...... 70 LED2_3 ...... 71 LED2_2 ...... 72 LED2_1 ...... 73 GNDIO ...... 74 LED1_3 ...... 75 LED1_2 ...... 76 LED1_1 ...... 77 VCCD ...... 78 GNDD ...... 79 LED0_3 ...... 80 LED0_2 ...... 81 LED0_1 ...... 82 AMDIX_EN ...... 83 MDDIS ...... 84 CFG_3 ...... 85 CFG_2 ...... 86 CFG_1 ...... 87 ADD_4 ...... 88 ADD_3 ...... 89 ADD_2 ...... 90 ADD_1 ...... 91 ADD_0 ...... 92 TxSlew_1 ...... 93 TxSlew_0 ...... 94 SD_2P5V ...... 95 SD0 ...... 96 SD1 ...... 97 VCCPECL ...... 98 GNDPECL ...... 99 SD2 ...... 100 SD3 ...... 101 N/C ...... 102 VCCR0 ...... 103 TPFIP0 ...... 104
208 ........ VCCIO 207 ........ GNDIO 206 ........ RxData6_0 205 ........ RxData6_1 204 ........ TxData7_1 203 ........ TxData7_0 202 ........ TxEN7 201 ........ RxER7 200 ........ CRS_DV7 199 ........ GNDIO 198 ........ RxData7_0 197 ........ RxData7_1 196 ........ VCCD 195 ........ GNDD 194 ........ LED7_3 193 ........ LED7_2 192 ........ LED7_1 191 ........ LED6_3 190 ........ LED6_2 189 ........ LED6_1 188 ........ GNDIO 187 ........ LED5_3 186 ........ LED5_2 185 ........ LED5_1 184 ........ VCCD 183 ........ GNDD 182 ........ LED4_3 181 ........ LED4_2 180 ........ LED4_1 179 ........ SGND 178 ........ ModeSel1 177 ........ ModeSel0 176 ........ Section 175 ........ RESET 174 ........ PWRDWN 173 ........ G_FX/TP 172 ........ N/C 171....... TRST 170 ........ TCK 169 ........ TMS 168 ........ TDO 167 ........ TDI 166 ........ SD7 165 ........ SD6 164 ........ VCCPECL 163 ........ GNDPECL 162 ........ SD5 161 ........ SD4 160 ........ N/C 159 ........ N/C 158 ........ VCCR7 157 ........ TPFIP7
Part # LOT # FPO #
LXT9785/9785E XX XXXXXX XXXXXXXX
Rev #
156 .........TPFIN7 155 .........GNDR7 154 .........TPFOP7 153 .........TPFON7 152 .........VCCT6/7 151 .........TPFON6 150 .........TPFOP6 149 .........GNDR6 148 .........GNDT6/7 147 .........TPFIN6 146 .........TPFIP6 145 .........VCCR6 144 .........VCCR5 143 .........TPFIP5 142 .........TPFIN5 141 .........GNDR5 140 .........TPFOP5 139 .........TPFON5 138 .........VCCT4/5 137 .........TPFON4 136 .........TPFOP4 135 .........GNDR4 134 .........GNDT4/5 133 .........TPFIN4 132 .........TPFIP4 131 .........VCCR4 130 .........VCCR3 129 .........TPFIP3 128 .........TPFIN3 127 .........GNDT2/3 126 .........GNDR3 125 .........TPFOP3 124 .........TPFON3 123 .........VCCT2/3 122 .........TPFON2 121 .........TPFOP2 120 .........GNDR2 119 .........TPFIN2 118 .........TPFIP2 117 .........VCCR2 116 .........VCCR1 115 .........TPFIP1 114 .........TPFIN1 113 .........GNDT0/1 112 .........GNDR1 111 .........TPFOP1 110 .........TPFON1 109 .........VCCT0/1 108 .........TPFON0 107 .........TPFOP0 106 .........GNDR0 105 .........TPFIN0
21
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 2.
Intel(R) LXT9785/LXT9785E RMII PQFP Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Symbol CRS_DV6 RxER6/ LINKHOLD TxEN6 TxData6_0 TxData6_1 REFCLK1 RxData5_1 RxData5_0 GNDIO CRS_DV5 RxER5 / FIFOSEL1 TxEN5 TxData5_0 TxData5_1 RxData4_1 RxData4_0 CRS_DV4 VCCIO GNDIO RxER4 / FIFOSEL0 TxEN4 TxData4_0 TxData4_1 MDC1 MDIO1 MDINT1 RxData3_1 RxData3_0 VCCIO Type O, TS, SL O, TS, SL, ID, I, ST I, ID I, ID I, ID I O, TS, ID O, TS - O, TS, SL O, TS, SL, ID, I, ST I, ID I, ID I, ID O, TS,ID O, TS O, TS, SL - - O, TS, SL, ID, I, ST I, ID I, ID I, ID I, ST, ID I/O, TS, SL, IP OD, TS, SL, IP O, TS, ID O, TS - Reference for Full Description Table 5 (page 36) Table 5 (page 36) 32 Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) 36 Table 5 (page 36) 37 Table 5 (page 36) Table 15 (page 48) 39 Table 5 (page 36) 40 Table 5 (page 36) 41 Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 8 (page 40) 54 Table 8 (page 40) 55 Table 8 (page 40) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) 56 57 58 RxData0_0 VCCIO GNDIO CRS_DV0 RxData0_1 42 43 44 45 46 47 48 49 50 51 52 53 RxER2 (PREASEL) TxEN2 TxData2_0 TxData2_1 REFCLK0 RxData1_1 RxData1_0 VCCIO GNDIO CRS_DV1 RxER1/ PAUSE TxEN1 TxData1_0 TxData1_1 CRS_DV2 38 RxData2_0 GNDIO RxData2_1 33 34 35 RxER3 TxEN3 TxData3_0 TxData3_1 Pin 30 31 Symbol GNDIO CRS_DV3 Type - O, TS, SL O, TS, SL, ID I, ID I, ID I, ID O, TS, ID O, TS - O, TS, SL O, TS, SL, ID, I, ST I, ID I, ID I, ID I O, TS, ID O, TS - - O, TS, SL O, TS, SL, ID, I, ST I, ID I, ID I, ID O, TS, ID O, TS - - O, TS, SL Reference for Full Description Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 15 (page 48) Table 5 (page 36)
22
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol RxER0/ MDIX TxEN0 TxData0_0 TxData0_1 MDC0 MDIO0 VCCD GNDD MDINT0 LED3_3 LED3_2 LED3_1 LED2_3 LED2_2 LED2_1 GNDIO LED1_3 LED1_2 LED1_1 VCCD GNDD LED0_3 LED0_2 LED0_1 AMDIX_EN MDDIS CFG_3 CFG_2
Type O, TS, SL, ID, I, ST I, ID I, ID I, ID I, ST, ID I/O, TS, SL, IP - - OD, TS, SL, IP OD, TS, SO, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP I, ST, ID I, ST, ID I, ST, ID
Reference for Full Description Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 8 (page 40) Table 8 (page 40) Table 15 (page 48) Table 15 (page 48) Table 8 (page 40) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 13 (page 43) Table 9 (page 41) Table 13 (page 43) Table 13 (page 43)
Pin 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
Symbol CFG_1 ADD_4 ADD_3 ADD_2 ADD_1 ADD_0 TxSLEW_1 TxSLEW_0 SD_2P5V SD0 SD1 VCCPECL GNDPECL SD2 SD3 N/C VCCR0 TPFIP0 TPFIN0 GNDR0 TPFOP0 TPFON0 VCCT0/1 TPFON1 TPFOP1 GNDR1 GNDT0/1 TPFIN1 TPFIP1 VCCR1 VCCR2 TPFIP2 TPFIN2 GNDR2 TPFOP2 TPFON2 VCCT2/3 TPFON3
Type I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I I - - I I - - AO/AI AO/AI - AO/AI AO/AI - AO/AI AO/AI - - AO/AI AO/AI - - AO/AI AO/AI - AO/AI AO/AI - AO/AI
Reference for Full Description Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 10 (page 42) Table 10 (page 42) Table 10 (page 42) Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 17 (page 50) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42)
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
23
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
Symbol TPFOP3 GNDR3 GNDT2/3 TPFIN3 TPFIP3 VCCR3 VCCR4 TPFIP4 TPFIN4 GNDT4/5 GNDR4 TPFOP4 TPFON4 VCCT4/5 TPFON5 TPFOP5 GNDR5 TPFIN5 TPFIP5 VCCR5 VCCR6 TPFIP6 TPFIN6 GNDT6/7 GNDR6 TPFOP6 TPFON6 VCCT6/7 TPFON7 TPFOP7 GNDR7 TPFIN7 TPFIP7 VCCR7 N/C N/C SD4 SD5
Type AO/AI - - AO/AI AO/AI - - AO/AI AO/AI - - AO/AI AO/AI - AO/AI AO/AI - AO/AI AO/AI - - AO/AI AO/AI - - AO/AI AO/AI - AO/AI AO/AI - AO/AI AO/AI - - - I I
Reference for Full Description Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 17 (page 50) Table 17 (page 50) Table 10 (page 42) Table 10 (page 42)
Pin 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193
Symbol GNDPECL VCCPECL SD6 SD7 TDI TDO TMS TCK TRST N/C G_FX/TP PWRDWN RESET SECTION ModeSel0 ModeSel1 SGND LED4_1 LED4_2 LED4_3 GNDD VCCD LED5_1 LED5_2 LED5_3 GNDIO LED6_1 LED6_2 LED6_3 LED7_1 LED7_2
Type - - I I I, ST, IP O, TS I, ST, IP I, ST, ID I, ST, IP - I, ST, ID I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
Reference for Full Description Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 17 (page 50) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47)
24
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Symbol LED7_3 GNDD VCCD RxData7_1 RxData7_0 GNDIO CRS_DV7 RxER7 TxEN7 TxData7_0 TxData7_1 RxData6_1 RxData6_0 GNDIO VCCIO
Type OD, TS, SL, IP - - O, TS, ID O, TS - O, TS, SL O, TS, SL, ID I, ID I, ID I, ID O, TS, ID O, TS - -
Reference for Full Description Table 5 (page 36) Table 15 (page 48) Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 5 (page 36) Table 15 (page 48) Table 15 (page 48)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
25
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.2
PQFP Pin Assignments - SMII Configuration
Figure 3 and Table 3, "Intel(R) LXT9785/LXT9785E SMII PQFP Pin List" on page 27 provide the LXT9785/LXT9785E SMII PQFP pin assignments.
Figure 3. Intel(R) LXT9785/LXT9785E SMII 208-Pin PQFP Assignments
LINKHOLD
N/C.......1 .......2 N/C.......3 TxData6.......4 N/C.......5 REFCLK1.......6 N/C.......7 RxData5.......8 GNDIO.......9 N/C.......10 FIFOSEL1.......11 N/C.......12 TxData5.......13 N/C.......14 N/C.......15 RxData4.......16 N/C.......17 VCCIO.......18 GNDIO.......19 FIFOSEL0.......20 N/C.......21 TxData4.......22 N/C.......23 MDC1.......24 MDIO1.......25 MDINT1.......26 N/C.......27 RxData3.......28 VCCIO.......29 GNDIO.......30 N/C.......31 N/C.......32 N/C.......33 TxData3.......34 SYNC0.......35 N/C.......36 RxData2.......37 GNDIO.......38 N/C.......39 PREASEL.......40 N/C.......41 TxData2.......42 N/C.......43 REFCLK0.......44 N/C.......45 RxData1.......46 VCCIO.......47 GNDIO.......48 N/C.......49 PAUSE.......50 N/C.......51 TxData1.......52
26
N/C ...... 53 N/C ...... 54 RxData0 ...... 55 VCCIO ...... 56 GNDIO ...... 57 N/C ...... 58 MDIX ...... 59 N/C ...... 60 TxData0 ...... 61 N/C ...... 62 MDC0 ...... 63 MDIO0 ...... 64 VCCD ...... 65 GNDD ...... 66 MDINT0 ...... 67 LED3_3 ...... 68 LED3_2 ...... 69 LED3_1 ...... 70 LED2_3 ...... 71 LED2_2 ...... 72 LED2_1 ...... 73 GNDIO ...... 74 LED1_3 ...... 75 LED1_2 ...... 76 LED1_1 ...... 77 VCCD ...... 78 GNDD ...... 79 LED0_3 ...... 80 LED0_2 ...... 81 LED0_1 ...... 82 AMDIX_EN ...... 83 MDDIS ...... 84 CFG_3 ...... 85 CFG_2 ...... 86 CFG_1 ...... 87 ADD_4 ...... 88 ADD_3 ...... 89 ADD_2 ...... 90 ADD_1 ...... 91 ADD_0 ...... 92 TxSlew_1 ...... 93 TxSlew_0 ...... 94 SD_2P5V ...... 95 SD0 ...... 96 SD1 ...... 97 VCCPECL ...... 98 GNDPECL ...... 99 SD2 ...... 100 SD3 ...... 101 N/C ...... 102 VCCR0 ...... 103 TPFIP0 ...... 104
208 ........ VCCIO 207 ........ GNDIO 206 ........ RxData6 205 ........ N/C 204 ........ SYNC1 203 ........ TxData7 202 ........ N/C 201 ........ N/C 200 ........ N/C 199 ........ GNDIO 198 ........ RxData7 197 ........ N/C 196 ........ VCCD 195 ........ GNDD 194 ........ LED7_3 193 ........ LED7_2 192 ........ LED7_1 191 ........ LED6_3 190 ........ LED6_2 189 ........ LED6_1 188 ........ GNDIO 187 ........ LED5_3 186 ........ LED5_2 185 ........ LED5_1 184 ........ VCCD 183 ........ GNDD 182 ........ LED4_3 181 ........ LED4_2 180 ........ LED4_1 179 ........ SGND 178 ........ ModeSel_1 177 ........ ModeSel_0 176 ........ Section 175 ........ RESET 174 ........ PWRDWN 173 ........ G_FX/TP 172 ........ N/C 171....... TRST 170 ........ TCK 169 ........ TMS 168 ........ TDO 167 ........ TDI 166 ........ SD7 165 ........ SD6 164 ........ VCCPECL 163 ........ GNDPECL 162 ........ SD5 161 ........ SD4 160 ........ N/C 159 ........ N/C 158 ........ VCCR7 157 ........ TPFIP7
Part # LOT # FPO #
LXT9785/9785E XX XXXXXX XXXXXXXX
Rev #
156 ........ TPFIN7 155 ........ GNDR7 154 ........ TPFOP7 153 ........ TPFON7 152 ........ VCCT6/7 151 ........ TPFON6 150 ........ TPFOP6 149 ........ GNDR6 148 ........ GNDT6/7 147 ........ TPFIN6 146 ........ TPFIP6 145 ........ VCCR6 144 ........ VCCR5 143 ........ TPFIP5 142 ........ TPFIN5 141 ........ GNDR5 140 ........ TPFOP5 139 ........ TPFON5 138 ........ VCCT4/5 137 ........ TPFON4 136 ........ TPFOP4 135 ........ GNDR4 134 ........ GNDT4/5 133 ........ TPFIN4 132 ........ TPFIP4 131 ........ VCCR4 130 ........ VCCR3 129 ........ TPFIP3 128 ........ TPFIN3 127 ........ GNDT2/3 126 ........ GNDR3 125 ........ TPFOP3 124 ........ TPFON3 123 ........ VCCT2/3 122 ........ TPFON2 121 ........ TPFOP2 120 ........ GNDR2 119 ........ TPFIN2 118 ........ TPFIP2 117 ........ VCCR2 116 ........ VCCR1 115 ........ TPFIP1 114 ........ TPFIN1 113 ........ GNDT0/1 112 ........ GNDR1 111 ........ TPFOP1 110 ........ TPFON1 109 ........ VCCT0/1 108 ........ TPFON0 107 ........ TPFOP0 106 ........ GNDR0 105 ........ TPFIN0
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 3.
Intel(R) LXT9785/LXT9785E SMII PQFP Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol N/C N/C (LINKHOLD) N/C TxData6 N/C REFCLK1 N/C RxData5 GNDIO N/C FIFOSEL1 N/C TxData5 N/C N/C RxData4 N/C VCCIO GNDIO FIFOSEL0 N/C TxData4 N/C MDC1 MDIO1 MDINT1 N/C RxData3 VCCIO GNDIO N/C N/C N/C Type1 - - I, ID, - I, ID - I - O, TS - - I, ID, ST - I, ID - - O, TS - - - I, ID, ST I, ID I, ID - I, ST, ID I/O, TS, SL, IP OD, TS, SL, IP - O, TS - - - - - Reference for Full Description Table 16 (page 50) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 5 (page 36) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 9 (page 41) Table 9 (page 41) Table 9 (page 41) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 16 (page 50) 65 66 67 VCCD GNDD MDINT0 Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol TxData3 SYNC0 N/C RxData2 GNDIO N/C PREASEL N/C TxData2 N/C REFCLK0 N/C RxData1 VCCIO GNDIO N/C PAUSE N/C TxData1 N/C N/C RxData0 VCCIO GNDIO N/C MDIX N/C TxData0 N/C MDC0 MDIO0 Type1 I, ID I, ID - O, TS - - I, ID, ST - I, ID - I - O, TS - - - I, ID, ST - I, ID - - O, TS - - - I, ID, ST - I, ID - I, ST, ID I/O, TS, SL, IP - - OD, TS, SL, IP Reference for Full Description Table 6 (page 39) Table 7 (page 39) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 5 (page 36) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 9 (page 41) Table 9 (page 41) Table 15 (page 48) Table 15 (page 48) Table 9 (page 41)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
27
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type1 OD, TS, SO, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID
Reference for Full Description Table 14 (page 47)
Pin 92 93 94
Symbol ADD_0 TxSLEW_1 TxSLEW_0 SD_2P5V SD0 SD1 VCCPECL GNDPECL SD2 SD3 N/C VCCR0 TPFIP0 TPFIN0 GNDR0 TPFOP0 TPFON0 VCCT0/1 TPFON1 TPFOP1 GNDR1 GNDT0/1 TPFIN1 TPFIP1 VCCR1 VCCR2 TPFIP2 TPFIN2 GNDR2 TPFOP2 TPFON2 VCCT2/3 TPFON3 TPFOP3 GNDR3 GNDT2/3 TPFIN3 TPFIP3
Type1
Reference for Full Description
I, ST, ID Table 13 (page 43) I, ST, ID I, ST, ID Table 13 (page 43) Table 13 (page 43)
68
LED3_3
69
LED3_2
Table 14 (page 47)
95 96
I, ST, ID Table 10 (page 42) I I - - I I - - AI/AO AI/AO - AO/AI AO/AI - AO/AI AO/AI - - AI/AO AI/AO - - AI/AO AI/AO - AO/AI AO/AI - AO/AI AO/AI - - AI/AO AI/AO Table 10 (page 42) Table 10 (page 42) Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 17 (page 50) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42)
70
LED3_1
Table 14 (page 47)
97 98
71
LED2_3
Table 14 (page 47)
99 100
72
LED2_2
Table 14 (page 47)
101 102 103
73 74 75
LED2_1 GNDIO LED1_3
Table 14 (page 47) Table 15 (page 48) Table 14 (page 47)
104 105 106 107 108
76
LED1_2
Table 14 (page 47)
109 110
77 78 79 80
LED1_1 VCCD GNDD LED0_3
Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47)
111 112 113 114 115 116 117
81
LED0_2
Table 14 (page 47)
118 119
82 83 84 85 86 87 88 89 90 91
LED0_1 AMDIX_EN MDDIS CFG_3 CFG_2 CFG_1 ADD_4 ADD_3 ADD_2 ADD_1
Table 14 (page 47) Table 13 (page 43) Table 8 (page 40) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43)
120 121 122 123 124 125 126 127 128 129
28
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167
Symbol VCCR3 VCCR4 TPFIP4 TPFIN4 GNDT4/5 GNDR4 TPFOP4 TPFON4 VCCT4/5 TPFON5 TPFOP5 GNDR5 TPFIN5 TPFIP5 VCCR5 VCCR6 TPFIP6 TPFIN6 GNDT6/7 GNDR6 TPFOP6 TPFON6 VCCT6/7 TPFON7 TPFOP7 GNDR7 TPFIN7 TPFIP7 VCCR7 N/C N/C SD4 SD5 GNDPECL VCCPECL SD6 SD7 TDI
Type1 - - AI/AO AI/AO - - AO/AI AO/AI - AO/AI AO/AI - AI/AO AI/AO - - AI/AO AI/AO - - AO/AI AO/AI - AO/AI AO/AI - AI/AO AI/AO - - - I I - - I I I, ST, IP
Reference for Full Description Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 17 (page 50) Table 17 (page 50) Table 10 (page 42) Table 10 (page 42) Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 12 (page 43)
Pin 168 169 170 171 172 173 174 175 176 177 178 179 180
Symbol TDO TMS TCK TRST N/C G_FX/TP PWRDWN RESET Section ModeSel0 ModeSel1 SGND LED4_1
Type1 O, TS I, ST, IP I, ST, ID I, ST, IP - I, ST, ID I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
Reference for Full Description Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 17 (page 50) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 15 (page 48) Table 14 (page 47)
181
LED4_2
Table 14 (page 47)
182 183 184 185
LED4_3 GNDD VCCD LED5_1
Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47)
186
LED5_2
Table 14 (page 47)
187 188 189
LED5_3 GNDIO LED6_1
Table 14 (page 47) Table 15 (page 48) Table 14 (page 47)
190
LED6_2
Table 14 (page 47)
191
LED6_3
Table 14 (page 47)
192
LED7_1
Table 14 (page 47)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
29
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin
Symbol
Type1 OD, TS, SL, IP OD, TS, SL, IP - - O, TS, ID O, TS - - - - I, ID I, ID - O, TS - -
Reference for Full Description Table 14 (page 47)
193
LED7_2
194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
LED7_3 GNDD VCCD N/C RxData7 GNDIO N/C N/C N/C TxData7 SYNC1 N/C RxData6 GNDIO VCCIO
Table 5 (page 36) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 16 (page 50) Table 6 (page 39) Table 5 (page 36) Table 16 (page 50) Table 6 (page 39) Table 15 (page 48) Table 15 (page 48)
30
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.1.3
PQFP Pin Assignments - SS-SMII Configuration
Figure 4 and Table 4, "Intel(R) LXT9785/LXT9785 SS-SMII PQFP Pin List" on page 32 provide the LXT9785/LXT9785E SS-SMII PQFP pin assignments.
Figure 4. Intel(R) LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments
N/C ......1 N/CLINKHOLD ...... 2 N/C ......3 TxData6 ...... 4 N/C ......5 REFCLK1 ......6 RxData5 ......7 N/C ......8 GNDIO ......9 N/C ......10 FIFOSEL1 ...... 11 N/C ......12 TxData5 ......13 N/C ......14 RxData4 ......15 N/C ......16 RxSYNC1 ......17 VCCIO ......18 GNDIO ......19 FIFOSEL0 ...... 20 RxCLK1 ......21 TxData4 ......22 N/C ......23 MDC1 ......24 MDIO1 ...... 25 MDINT1 ......26 RxData3 ......27 N/C ......28 VCCIO ......29 GNDIO ......30 N/C ......31 TxCLK0 ......32 N/C ......33 TxData3 ......34 TxSYNC0 ......35 RxData2 ......36 N/C ......37 GNDIO ......38 N/C ......39 PREASEL ......40 N/C ......41 TxData2 ......42 N/C ......43 REFCLK0 ......44 RxData1 ......45 N/C ......46 VCCIO ......47 GNDIO ......48 N/C ......49 PAUSE ......50 N/C ......51 TxData1 ......52
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
N/C...... 53 RxData0...... 54 N/C...... 55 VCCIO...... 56 GNDIO...... 57 RxSYNC0...... 58 MDIX...... 59 RxCLK0...... 60 TxData0...... 61 N/C...... 62 MDC0...... 63 MDIO0...... 64 VCCD...... 65 GNDD...... 66 MDINT0...... 67 LED3_3...... 68 LED3_2...... 69 LED3_1...... 70 LED2_3...... 71 LED2_2...... 72 LED2_1...... 73 GNDIO...... 74 LED1_3...... 75 LED1_2...... 76 LED1_1...... 77 VCCD...... 78 GNDD...... 79 LED0_3...... 80 LED0_2...... 81 LED0_1...... 82 AMDIX_EN...... 83 MDDIS...... 84 CFG_3...... 85 CFG_2...... 86 CFG_1...... 87 ADD_4...... 88 ADD_3...... 89 ADD_2...... 90 ADD_1...... 91 ADD_0...... 92 TxSlew_1...... 93 TxSlew_0...... 94 SD_2P5V...... 95 SD0...... 96 SD1...... 97 VCCPECL...... 98 GNDPECL...... 99 SD2...... 100 SD3...... 101 N/C...... 102 VCCR0...... 103 TPFIP0...... 104
208 ......... VCCIO 207 ......... GNDIO 206 ......... N/C 205 ......... RxData6 204 ......... TxSYNC1 203 ......... TxData7 202 ......... N/C 201 ......... TxCLK1 200 ......... N/C 199 ......... GNDIO 198 ......... N/C 197 ......... RxData7 196 .........VCCD 195 ......... GNDD 194 ......... LED7_3 193 ......... LED7_2 192 ......... LED7_1 191 ......... LED6_3 190 ......... LED6_2 189 ......... LED6_1 188 ......... GNDIO 187 ......... LED5_3 186 ......... LED5_2 185 ......... LED5_1 184 ......... VCCD 183 ......... GNDD 182 ......... LED4_3 181 ......... LED4_2 180 ......... LED4_1 179 ......... SGND 178 ......... ModeSel_1 177 ......... ModeSel_0 176 ......... Section 175 ......... RESET 174 ......... PWRDWN 173 ......... G_FX/TP 172 ......... N/C 171....... TRST 170 ......... TCK 169 ......... TMS 168 ......... TDO 167 ......... TDI 166 ......... SD7 165 ......... SD6 164 ......... VCCPECL 163 ......... GNDPECL 162 ......... SD5 161 ......... SD4 160 ......... N/C 159 ......... N/C 158 ......... VCCR7 157 ......... TPFIP7
Part # LOT # FPO #
LXT9785/9785E XX XXXXXX XXXXXXXX
Rev #
156.........TPFIN7 155.........GNDR7 154......... TPFOP7 153.........TPFON7 152......... VCCT6/7 151.........TPFON6 150......... TPFOP6 149.........GNDR6 148......... GNDT6/7 147......... TPFIN6 146......... TPFIP6 145.........VCCR6 144.........VCCR5 143......... TPFIP5 142......... TPFIN5 141.........GNDR5 140......... TPFOP5 139.........TPFON5 138......... VCCT4/5 137.........TPFON4 136......... TPFOP4 135.........GNDR4 134......... GNDT4/5 133......... TPFIN4 132......... TPFIP4 131.........VCCR4 130.........VCCR3 129......... TPFIP3 128......... TPFIN3 127......... GNDT2/3 126.........GNDR3 125......... TPFOP3 124.........TPFON3 123......... VCCT2/3 122.........TPFON2 121......... TPFOP2 120.........GNDR2 119......... TPFIN2 118......... TPFIP2 117.........VCCR2 116.........VCCR1 115......... TPFIP1 114......... TPFIN1 113......... GNDT0/1 112.........GNDR1 111......... TPFOP1 110.........TPFON1 109......... VCCT0/1 108.........TPFON0 107......... TPFOP0 106.........GNDR0 105......... TPFIN0
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 4.
Intel(R) LXT9785/LXT9785 SS-SMII PQFP Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol N/C N/C LINKHOLD N/C TxData6 N/C REFCLK1 RxData5 N/C GNDIO N/C FIFOSEL1 N/C TxData5 N/C RxData4 N/C RxSYNC1 VCCIO GNDIO FIFOSEL0 RxCLK1 TxData4 N/C MDC1 MDIO1 MDINT1 RxData3 N/C VCCIO GNDIO N/C TxCLK0 - I, ID I I O, TS, ID - - - I, ID, ST - I, ID - O, TS, ID - O, TS, ID - - I, ID, ST O, TS, ID I, ID - I, ST, ID I/O, TS, SL, IP OD, TS, SL, IP O, TS, ID - - - - I, ID Type1 - Reference for Full Description Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 6 (page 39) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 8 (page 40) Table 16 (page 50) Table 8 (page 40) Table 15 (page 48) Table 15 (page 48) Table 13 (page 43) Table 8 (page 40) Table 6 (page 39) Table 16 (page 50) Table 9 (page 41) Table 9 (page 41) Table 9 (page 41) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 8 (page 40) 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 RxData1 N/C VCCIO GNDIO N/C PAUSE N/C TxData1 N/C RxData0 N/C VCCIO GNDIO RxSYNC0 MDIX RxCLK0 TxData0 N/C MDC0 MDIO0 VCCD GNDD 36 37 38 39 40 41 42 43 44 RxData2 N/C GNDIO N/C PREASEL N/C TxData2 N/C REFCLK0 Pin 33 34 35 Symbol N/C TxData3 TxSYNC0 Type1 - I, ID I, ID O, TS, ID - - - I, ST - I, ID - I O, TS, ID - - - - I, ID, ST - I, ID - O, TS, ID - - - O, TS, ID I, ID, ST - I, ID - I, ST, ID I/O, TS, SL, IP - - Reference for Full Description Table 16 (page 50) Table 6 (page 39) Table 8 (page 40) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 6 (page 39) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 15 (page 48) Table 16 (page 50) Table 13 (page 43) Table 16 (page 50) Table 6 (page 39) Table 16 (page 50) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 15 (page 48) Table 8 (page 40) Table 13 (page 43) Table 8 (page 40) Table 6 (page 39) Table 16 (page 50) Table 9 (page 41) Table 9 (page 41) Table 15 (page 48) Table 15 (page 48)
32
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
Symbol MDINT0 LED3_3 LED3_2 LED3_1 LED2_3 LED2_2 LED2_1 GNDIO LED1_3 LED1_2 LED1_1 VCCD GNDD LED0_3 LED0_2 LED0_1 AMDIX_EN MDDIS CFG_3 CFG_2 CFG_1 ADD_4 ADD_3 ADD_2 ADD_1 ADD_0 TxSLEW_1 TxSLEW_0 SD_2P5V SD0
Type1 OD, TS, SL, IP OD, TS, SO, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I
Reference for Full Description Table 9 (page 41) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 13 (page 43) Table 9 (page 41) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 10 (page 42) Table 10 (page 42)
Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134
Symbol SD1 VCCPECL GNDPECL SD2 SD3 N/C VCCR0 TPFIP0 TPFIN0 GNDR0 TPFOP0 TPFON0 VCCT0/1 TPFON1 TPFOP1 GNDR1 GNDT0/1 TPFIN1 TPFIP1 VCCR1 VCCR2 TPFIP2 TPFIN2 GNDR2 TPFOP2 TPFON2 VCCT2/3 TPFON3 TPFOP3 GNDR3 GNDT2/3 TPFIN3 TPFIP3 VCCR3 VCCR4 TPFIP4 TPFIN4 GNDT4/5
Type1 I - - I I - - AI/AO AI/AO - AO/AI AO/AI - AO/AI AO/AI - - AI/AO AI/AO - - AI/AO AI/AO - AO/AI AO/AI - AO/AI AO/AI - - AI/AO AI/AO - - AI/AO AI/AO -
Reference for Full Description Table 10 (page 42) Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 16 (page 50) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
33
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172
Symbol GNDR4 TPFOP4 TPFON4 VCCT4/5 TPFON5 TPFOP5 GNDR5 TPFIN5 TPFIP5 VCCR5 VCCR6 TPFIP6 TPFIN6 GNDT6/7 GNDR6 TPFOP6 TPFON6 VCCT6/7 TPFON7 TPFOP7 GNDR7 TPFIN7 TPFIP7 VCCR7 N/C N/C SD4 SD5 GNDPECL VCCPECL SD6 SD7 TDI TDO TMS TCK TRST N/C
Type1 - AO/AI AO/AI - AO/AI AO/AI - AI/AO AI/AO - - AI/AO AI/AO - - AO/AI AO/AI - AO/AI AO/AI - AI/AO AI/AO - - - I I - - I I I, ST, IP O, TS I, ST, IP I, ST, ID I, ST, IP -
Reference for Full Description Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 11 (page 42) Table 11 (page 42) Table 15 (page 48) Table 16 (page 50) Table 16 (page 50) Table 10 (page 42) Table 10 (page 42) Table 15 (page 48) Table 15 (page 48) Table 10 (page 42) Table 10 (page 42) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 12 (page 43) Table 16 (page 50)
Pin 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
Symbol G_FX/TP PWRDWN RESET SECTION ModeSel0 ModeSel1 SGND LED4_1 LED4_2 LED4_3 GNDD VCCD LED5_1 LED5_2 LED5_3 GNDIO LED6_1 LED6_2 LED6_3 LED7_1 LED7_2 LED7_3 GNDD VCCD RxData7 N/C GNDIO N/C TxCLK1 N/C
Type1 I, ST, ID I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - O, TS, ID - - - I, ID -
Reference for Full Description Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 13 (page 43) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 14 (page 47) Table 15 (page 48) Table 15 (page 48) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 16 (page 50) Table 8 (page 40) Table 16 (page 50)
34
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Pin 203 204 205 206 207 208
Symbol TxData7 TxSYNC1 RxData6 N/C GNDIO VCCIO
Type1 I, ID I, ID O, TS, ID - - -
Reference for Full Description Table 6 (page 39) Table 8 (page 40) Table 8 (page 40) Table 16 (page 50) Table 15 (page 48) Table 15 (page 48)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
35
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.2
3.2.1
PQFP Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the two designations. Signal naming conventions are as follows:
* Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
* Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
* Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.
3.2.2
PQFP Signal Descriptions - RMII, SMII, and SS-SMII Configurations
Table 5 through Table 17, "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations" on page 50 provide PQFP signal descriptions. Ball designations are included for cross-reference.
Table 5.
Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP (Sheet 1 of 3)
Pin-Ball Designation PQFP PBGA Reference Clock. 44 6 E6, E12 REFCLK0 REFCLK1 I 50 MHz RMII reference clock is always required. RMII inputs are sampled on the rising edge of REFCLK, RMII outputs are sourced on the falling edge. See "Clock/SYNC Requirements" on page 125 for detailed CLK requirements. Transmit Data - Port 0. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 0 are clocked in synchronously to REFCLK. Transmit Data - Port 1. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 1 are clocked in synchronously to REFCLK Transmit Data - Port 2. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 2 are clocked in synchronously to REFCLK. Symbol Type1 Signal Description2,3
61 62 52 53 42 43
E2, F4 C3, D4 B5 A4
TxData0_0 TxData0_1 TxData1_0 TxData1_1 TxData2_0 TxData2_1
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 5.
Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP (Sheet 2 of 3)
Pin-Ball Designation PQFP 34 35 22 23 13 14 4 5 203 204 60 51 41 33 21 12 3 202 55 54 46 45 37 36 28 27 16 15 8 7 PBGA D8, A6 A11, C10 B13, D11 D13, A16 E14, C16 E3, B2, C6, A7, B11, A14, C14, D16 C2, B1 A3, B4 B6, C7 D9, B9 A13, C12 B14, B15 TxData3_0 TxData3_1 TxData4_0 TxData4_1 TxData5_0 TxData5_1 TxData6_0 TxData6_1 TxData7_0 TxData7_1 TxEN0 TxEN1 TxEN2 TxEN3 TxEN4 TxEN5 TxEN6 TxEN7 RxData0_0 RxData0_1 RxData1_0 RxData1_1 RxData2_0 RxData2_1 RxData3_0 RxData3_1 RxData4_0 RxData4_1 RxData5_0 RxData5_1 Transmit Data - Port 3. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to REFCLK. Transmit Data - Port 4. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to REFCLK. Transmit Data - Port 5. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to REFCLK. Transmit Data - Port 6. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to REFCLK. Transmit Data - Port 7. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to REFCLK. Symbol Type1 Signal Description2,3
Transmit Enable - Ports 0-7. I, ID Active High input enables respective port transmitter. This signal must be synchronous to the REFCLK.
O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID
Receive Data - Port 0. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 1. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 2. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 3. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 4. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
37
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 5.
Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP (Sheet 3 of 3)
Pin-Ball Designation PQFP 206 205 198 197 58 49 39 31 17 10 1 200 PBGA C15, B17 E16, F14 E4, C4, A5, B8, B12, D12, B16, E15 RxData6_0 RxData6_1 RxData7_0 RxData7_1 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 O, TS O, TS, ID O, TS O, TS, ID Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Carrier Sense/Receive Data Valid - Ports 0-7. O, TS, SL, ID On detection of valid carrier, these signals are asserted asynchronously with respect to REFCLK. CRS_DVn is de-asserted on loss of carrier, synchronous to REFCLK. Receive Error - Ports 0-7. These signals are synchronous to the respective REFCLK. Active High indicates that received code group is invalid, or that PLL is not locked. O, TS, SL, ID The RxER signals have the following additional function pins: RxER0 (MDIX) RxER1 (PAUSE) RxER2 (PREASEL) RxER4 (FIFOSEL0) RxER5 (FIFOSEL1) RxER6 (LINKHOLD) 1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. Symbol Type1 Signal Description2,3
59 50 40 32 20 11 2 201
D2, D5, D7, C8, A12, A15, A17, D17
RxER0 RxER1 RxER2 RxER3 RxER4 RxER5 RxER6 RxER7
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 6.
Intel(R) LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions - PQFP
Pin/Ball Designation PQFP 61 52 42 34 22 13 4 203 PBGA E2, C3, B5, D8, A11, B13, D13, E14 E6, E12 TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 Symbol Type1 Signal Description2
Transmit Data - Ports 0-7. I, ID These serial input streams provide data to be transmitted to the network. The LXT9785/9785E clocks the data in synchronously to REFCLK.
Reference Clock. 44 6 REFCLK0 REFCLK1 I The LXT9785/9785E always requires a 125 MHz reference clock input. Refer to Functional Description for detailed clock requirements. REFCLK0 and REFCLK1 are always connected regardless of sectionalization mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 7.
Intel(R) LXT9785/LXT9785E SMII Specific Signal Descriptions - PQFP
Pin/Ball Designation PQFP PBGA SMII Synchronization. 35 204 A6, C16 SYNC0 SYNC1 I, ID The MAC must generate a SYNC pulse every 10 REFCLK cycles to synchronize the SMII. SYNC0 is used when 1x8 port sectionalization is selected. SYNC0 and SYNC1 are to be used when 2x4 port sectionalization is chosen. Symbol Type1 Signal Description2,3
55 46 37 28 16 8 206 198
C2, A3, B6, D9, A13, B14, C15, E16
RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7
Receive Data - Ports 0-7. O, TS These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. 3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware reset.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 8.
Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - PQFP
Pin/Ball Designation PQFP 35 204 PBGA SS-SMII Transmit Synchronization. A6, C16 TxSYNC0 TxSYNC1 I, ID The MAC must generate a TxSYNC pulse every 10 TxCLK cycles to mark the start of TxData segments. TxSYNC0 is used when 1x8 port sectionalization is selected. SS-SMII Receive Synchronization. 58 17 E4, B12 RxSYNC0 RxSYNC1 O, TS, ID The LXT9785/9785E generates these pulses every 10 RxCLK cycles to mark the start of RxData segments for the MAC. RxSYNC1 is used when 1x8 port sectionalization is selected. RxSYNC0 may not be used. These outputs are only enabled when SS-SMII mode is enabled. SS-SMII Transmit Clock. 32 201 C8, D17 TxCLK0 TxCLK1 I, ID The MAC sources this 125 MHz clock as the timing reference for TxData and TxSYNC. Only TxCLK0 is used when 1x8 port sectionalization is selected. See "Clock/ SYNC Requirements" on page 125 for detailed clock requirements. SS-SMII Receive Clock. 60 21 E3, B11 RxCLK0 RxCLK1 O, TS, ID The LXT9785/9785E generates these clocks, based on REFCLK, to provide a timing reference for RxData and RxSYNC to the MAC. RxCLK1 is used when 1x8 port sectionalization is selected. RxCLK0 may not be used. See "Clock/SYNC Requirements" on page 125 for detailed clock requirements. These outputs are only enabled when SSSMII mode is enabled. Symbol Type1 Signal Description2,3
54 45 36 27 15 7 205 197
B1, B4, C7, B9, C12, B15, B17, F14
RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7
Receive Data - Ports 0-7. O, TS, ID These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 9.
Intel(R) LXT9785/LXT9785E MDIO Control Interface Signals - PQFP
Pin/Ball Designation PQFP PBGA Management Data Input/Output. 64 25 F3, A10 MDIO0 MDIO1 I/O, TS, SL, IP Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7. Refer to Figure 21 on page 140. Management Data Interrupt. 67 26 F1, C9 MDINT0 MDINT1 OD,TS, SL, IP When Register bit 18.1 = 1, an active Low output on this Pin indicates status change. Only MDINT0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDINT0 is associated with ports 0-3 and MDINT1 is associated with ports 4-7. Refer to Figure 21 on page 140. Management Data Clock. 63 24 E1, B10 MDC0 MDC1 I, ST, ID Clock for the MDIO serial data channel. Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDC0 clocks ports 0-3 register accesses and MDC1 clocks ports 4-7 register accesses. Refer to Figure 21 on page 140. Management Disable. When MDDIS is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power up and reset. 84 L1 MDDIS I, ST, ID When MDDIS is pulled Low at power up or reset, via the internal pull-down resistor or by tieing it to ground, the Hardware Control Interface Pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. Symbol Type1 Signal Description2,3,4
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset. 4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15).
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 10. Intel(R) LXT9785/LXT9785E Signal Detect - PQFP
Pin/Ball Designation PQFP PBGA Signal Detect 2.5 Volt Interface. SD input threshold voltage select. 95 P1 SD_2P5V I, ST, ID Tie to VCCPECL = Select 2.5 V LVPECL input levels Float or Tie to GNDPECL = Select 3.3 V LVPECL input levels 96 97 100 101 161 162 165 166 P2, N4, P3, N5, P15, P16, P17, N17 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 Signal Detect - Ports 0-7. Signal Detect input from the fiber transceiver (these inputs are only active for ports operating in fiber mode). I Logic High = Normal operation (the process of searching for receive idles for the purpose of bringing link up is initiated) Logic Low = Link is declared lost Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. 3. Tie SD[0:7] inputs to GNDPECL if unused.
Table 11. Intel(R) LXT9785/LXT9785E Network Interface Signal Descriptions - PQFP
Pin/Ball Designation Symbol PQFP 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 PBGA T2, U1, T3, R4, T6, U5, U7, T7, T10, R10, T11, U11, T14,U15, R14, T15 R2, T1, U3, T4, R6, T5, T8, R8, T9, U9, U13, T12, R12, T13, R16, T16 TPFOP0, TPFON0 TPFOP1, TPFON1 TPFOP2, TPFON2 TPFOP3, TPFON3 TPFOP4, TPFON4 TPFOP5, TPFON5 TPFOP6, TPFON6 TPFOP7, TPFON7 TPFIP0, TPFIN0 TPFIP1, TPFIN1 TPFIP2, TPFIN2 TPFIP3, TPFIN3 TPFIP4, TPFIN4 TPFIP5, TPFIN5 TPFIP6, TPFIN6 TPFIP7, TPFIN7 Twisted-Pair/Fiber Outputs2, Positive & Negative, Ports 0-7. AO/AI During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFO pins produce differential LVPECL outputs for fiber transceivers. Twisted-Pair/Fiber Inputs3, Positive & Negative, Ports 0-7. AI/AO During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential 100BASE-TX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFI pins receive differential LVPECL inputs from fiber transceivers. Type1 Signal Description
1. Type Column Coding: AI = Analog Input, AO = Analog Output. 2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode]. 3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode].
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 12. Intel(R) LXT9785/LXT9785E JTAG Test Signal Descriptions - PQFP
Pin/Ball Designation PQFP 167 168 169 170 171 PBGA N14 N15 N16 M16 M17 TDI TDO TMS TCK TRST I, ST, IP O, TS I, ST, IP I, ST, ID I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for JTAG test. Test Reset. Reset input for JTAG test. Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT = Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. TDO output is three-stated in H/W Power-Down mode and during H/W reset.
Table 13. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP (Sheet 1 of 4)
Pin/Ball Designation PQFP PBGA Tx Output Slew Controls 0 and 1 Defaults. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 27.11:10 for all ports. These register bits can be read and overwritten after startup / reset. 94 93 N3, M4 TxSLEW_0 TxSLEW_1 These pins select the TX output slew rate for all ports (rise and fall time) as follows: I, ST, ID TxSLEW_1 0 0 1 1 TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 3.3 ns 3.6 ns 3.9 ns 4.2 ns Symbol Type1 Signal Description2
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP (Sheet 2 of 4)
Pin/Ball Designation PQFP PBGA Pause Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 4.10 for all ports. This register bit can be read and overwritten after startup / reset. 50 D5 PAUSE I, ID, ST When High, the LXT9785/9785E advertises Pause capabilities on all ports during auto-negotiation. This pin is shared with RMII-RxER1. An external pullup resistor (see applications section for value) can be used to set Pause active while RxER1 is three-stated during H/W reset. If no pull-up is used, the default Pause state is set inactive via the internal pull-down resistor. Power-Down. 174 L14 PWRDWN I, ST, ID When High, forces the LXT9785/9785E into global power-down mode. Pin is not on JTAG chain. Reset. 175 M15 RESET I, ST, IP This active low input is ORed with the control register Reset Register bit 0.15. When held Low, all outputs are forced to inactive state. Pin is not on JTAG chain. Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. I, ST, ID Port 0 Address = Base Port 1 Address = Base + 1 Port 2 Address = Base + 2 Port 3 Address = Base + 3 Port 4 Address = Base + 4 Port 5 Address = Base + 5 Port 6 Address = Base + 6 Port 7 Address = Base + 7 Mode Select[1:0]. 00 = RMII 178 177 L17, L16 MODESEL_1 MODESEL_0 01 = SMII I, ST, ID 10 = SS-SMII 11 = Reserved All ports are configured the same. Interfaces cannot be mixed and must be all RMII, SMII, or SS-SMII. Sectionalization Select. 176 L15 SECTION I, ST, ID This pin selects sectionalization into separate ports. 0 = 1x8 ports, 1 = 2x4 ports 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. Symbol Type1 Signal Description2
88 89 90 91 92
L4, M2, M3, N1, N2
ADD_4 ADD_3 ADD_2 ADD_1 ADD_0
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP (Sheet 3 of 4)
Pin/Ball Designation PQFP PBGA Auto MDIX Enable Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 27.9 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 40 on page 119. When active (High), automatic MDI crossover (MDIX) (regardless of segmentation) is selected for all ports. When inactive (Low) MDIX is selected according to the MDIX pin. MDIX Select Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 27.8 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 40, "Intel(R) LXT9785/LXT9785E MDIX Selection" on page 119. When AMDIX_EN is active this pin is ignored. 59 D2 MDIX I, ID, ST When AMDIX_EN is inactive, all ports are forced to the MDI or the MDIX function regardless of segmentation. If this pin is active (high), MDI crossover (MDIX) is selected. If this pin is inactive, non-crossover MDI mode is set. This pin is shared with RMII-RxER0. An external pullup resistor (see applications section for value) can be used to set MDIX active while RxER0 is three-stated during H/W reset. If no pull-up is used, the default MDIX state is set inactive via the internal pull-down resistor. Do not tie this pin directly to VCCIO (vs. using a pull-up) in non-RMII modes. Global Port Configuration Defaults 1-3. These pins are read at startup or reset. Their value at that time is used to set the default state of register bits shown in Table 42, "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129 for all ports. These register bits can be read and overwritten after startup / reset. When operating in Hardware Control Mode, these pins provide configuration control options for all the ports (refer to page 129 for details). Global FX/TP Enable Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 16.0 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 92, "Port Configuration Register (Address 16, Hex 10)" on page 207. This input selects whether all the ports are defaulted to TP vs. FX mode. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. Symbol Type1 Signal Description2
83
K1
AMDIX_EN
I, ST, IP
85 86 87
L2, L3, M1
CFG_3 CFG_2 CFG_1
I, ST, ID
173
M14
G_FX/TP
I, ST, ID
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 13. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP (Sheet 4 of 4)
Pin/Ball Designation PQFP PBGA FIFO Select <1:0>. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 18.15:14 for all ports. These register bits can be read and overwritten after startup/reset. 11 20 A15 A12 FIFOSEL1 FIFOSEL0 I, ID, ST These pins are shared with RMII-RxER<5:4>. An external pull-up resistor (see applications section for value) can be used to set FIFO Select<1:0> to active while RxER<5:4> are three-stated during hardware reset. If no pull-up is used, the default FIFO select state is set via the internal pull-down resistors. See Table 17, "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations" on page 50. Preamble Select. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 16.5 for all ports. This register bit can be read and overwritten after startup/reset. 40 D7 PREASEL I, ID, ST This pin is shared with RMII-RxER2. An external pullup resistor (see applications section for value) can be used to set Preamble Select to active while RxER2 is three-stated during hardware reset. If no pull-up is used, the default Preamble Select state is set via the internal pull-down resistors. Note: Preamble select has no effect in 100 Mbps operation. LINKHOLD Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 0.11 for all ports. This register bit can be read and overwritten after startup / reset. When High, the LXT9785/9785E powers down all ports. This pin is shared with RMII-RxER6. An external pullup resistor (see applications section for value) can be used to set LINKHOLD active while RxER6 is tri-stated during H/W reset. If no pull-up is used, the default LINKHOLD state is set inactive via the internal pulldown resistor. Symbol Type1 Signal Description2
2
A17
LINKHOLD
ID
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 14. Intel(R) LXT9785/LXT9785E LED Signal Descriptions - PQFP (Sheet 1 of 2)
Pin/Ball Designation PQFP PBGA Port 0 LED Drivers 1-3. 82 81 80 K3, K2, J1 LED0_1 LED0_2 LED0_3 OD, TS, SL, IP These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 1 LED Drivers 1-3. 77 76 75 J4, J3, H1 LED1_1 LED1_2 LED1_3 OD, TS, SL, IP These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 2 LED Drivers 1-3. 73 72 71 H2, H3, G1 LED2_1 LED2_2 LED2_3 OD, TS, SL, IP These pins drive LED indicators for Port 2. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 3 LED Drivers 1-3. 70 69 68 F2, G3, G4 LED3_1 LED3_2 LED3_3 OD, TS, SL, IP These pins drive LED indicators for Port 3. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 4 LED Drivers 1-3. 180 181 182 K16, K17, J17 LED4_1 LED4_2 LED4_3 OD, TS, SL, IP These pins drive LED indicators for Port 4. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. 4.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 14. Intel(R) LXT9785/LXT9785E LED Signal Descriptions - PQFP (Sheet 2 of 2)
Pin/Ball Designation PQFP PBGA Port 5 LED Drivers 1-3. 185 186 187 J15, J16, H17 LED5_1 LED5_2 LED5_3 OD, TS, SL, IP These pins drive LED indicators for Port 5. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 6 LED Drivers 1-3. 189 190 191 H15, H16, G17 LED6_1 LED6_2 LED6_3 OD, TS, SL, IP These pins drive LED indicators for Port 6. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 7 LED Drivers 1-3. 192 193 194 G15, F17, F16 LED7_1 LED7_2 LED7_3 OD, TS, SL, IP These pins drive LED indicators for Port 7. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. 4.
Table 15. Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - PQFP (Sheet 1 of 2)
Pin/Ball Designation Symbol PQFP 65, 78, 184, 196 PBGA G13, J14, F5, J5 VCCD Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. 18, 29, 47, 56, 208 A2, A8, C1, C11, D14 VCCIO +2.5/3.3 V supply for digital I/O circuits. The digital input circuits running off of this rail, having a TTL-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 V, when the IO supply is 3.3 V, and 2.5/3.3/5.0 V when 2.5 V. Digital Power Supply - PECL Signal Detect Inputs. 98, 164 L13, L5 VCCPECL +2.5/3.3 V supply for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these pins to GNDPECL to save power. Analog Power Supply - Receive. +2.5 V supply for all analog receive circuits. Type Signal Description
103, 116, 117, 130, 131, 144, 145, 158
N13, P4, P7, P8, P9, P10, P11, P12
VCCR
-
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 15. Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - PQFP (Sheet 2 of 2)
Pin/Ball Designation Symbol PQFP 109, 123, 138, 152 PBGA N6, N7, N9, N11, N12 A1, A9, B3, B7, C5, C13, C17, D1, D3, D6, D10, D15, E5, E7, E9, E11, E13, E17, F13, H8, H9, H10, J8, J9, J10, K8, K9, K10 VCCT Analog Power Supply - Transmit. +2.5 V supply for all analog transmit circuits. Type Signal Description
Digital Ground. GNDD Ground return for core digital supplies (VCCD). All ground pins can be tied together using a single ground plane.
66, 79, 183, 195
9, 19, 30, 38, 48, 57, 74, 188, 199, 207 99, 163 106, 112, 120, 126, 135, 141, 149, 155 M5, M13 P5, P6, P13, R7, R9, R11, R13, U8 P14, R1, R3, R5, R15, R17, T17, U2, U4, U6, U10, U12, U14, U16, U17 K14
GNDIO
-
Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO). Digital GND - PECL Signal Detect Inputs. Ground return for PECL Signal Detect input circuits. Analog Ground - Receive.
GNDPECL
-
GNDR
-
Ground return for receive analog supply. All ground pins can be tied together using a single ground plane.
113, 127, 134, 148
Analog Ground - Transmit. GNDT Ground return for transmit analog supply. All ground pins can be tied together using a single ground plane.
Substrate Ground. 179 SGND Ground for chip substrate. All ground pins can be tied together using a single ground plane.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 16. Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - PQFP
Pin/Ball Designation Symbol PQFP PBGA F15, G2, G5, G14, G16, H4, H14, J2, J13, K4, K15 Type1 Signal Description
N/C
N/C
-
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2.
Table 17. Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations
FIFOSEL1 0 0 1 1 FIFOSEL0 0 1 0 1 Register 18.15 Value 1 1 0 0 Register 18.14 Value 0 1 0 1
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Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3
BGA23 Ball Assignments
The following sections provide BGA23 ball location and signal description information for RMII, SMII, and SS-SMII:
* * * *
Table 3.3.1 "RMII BGA23 Ball List" on page 52 Table 3.3.2 "SMII BGA23 Ball List" on page 62 Table 3.3.3 "SS-SMII BGA23 Ball List" on page 72 Table 3.4 "BGA23 Signal Descriptions" on page 82
Figure 5 illustrates the LXT9785/LXT9785E 241-ball BGA23 ball locations for RMII, SMII, and SS-SMII. Figure 5. Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)
1 A B C D E F G H J K L M N P R T U
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1
2
A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2
3
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3
4
A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4
5
A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5
6
A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 L6 M6 N6 P6 R6 T6 U6
7
A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 N7 P7 R7 T7 U7
8
A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 N8 P8 R8 T8 U8
9
A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 L9 M9 N9 P9 R9 T9 U9
10
A10 B10
11
12
13
14
15
16
17 A B C D E F G H J K L M N P R T U
A11 A12 A13 A14 A15 B11 B12 B13 B14 B15
A16 A17 B16 B17
C10 C11 C12 C13 C14 C15 C16 C17 D10 D11 D12 D13 D14 D15 D16 D17 E10 F10 E11 E12 E13 E14 E15 F11 F12 F13 F14 F15 E16 E17 F16 F17
G10 G11 G12 G13 G14 G15 G16 G17 H10 H11 H12 H13 H14 H15 H16 H17 J10 J11 J12 J13 J14 J15 J16 J17
K10 K11 K12 K13 K14 K15 K16 K17 L10 L11 L12 L13 L14 L15 L16 L17
M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 P17 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17
U10 U11 U12 U13 U14 U15 U16 U17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
= No Ball
B1498-01
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
51
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.1
RMII BGA23 Ball List
The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows:
* Table 18 "Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
Signal Name"
* Table 19 "Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by
Ball Location" on page 57 Table 18. Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name
Signal ADD_0 ADD_1 ADD_2 ADD_3 ADD_4 AMDIX_EN CFG_1 CFG_2 CFG_3 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 G_FX/TP GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Ball Type1 N2 N1 M3 M2 L4 K1 M1 L3 L2 E4 C4 A5 B8 I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID O, TS, SL O, TS, SL O, TS, SL O, TS, SL Reference for Full Description Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Signal GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDPECL GNDPECL GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDR Ball Type1 D10 - D15 - E5 E7 E9 - - - Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
E11 - E13 - E17 - F13 - H8 H9 - -
H10 - J8 J9 J10 K8 K9 - - - - -
B12 O, TS, SL D12 O, TS, SL B16 O, TS, SL E15 O, TS, SL M14 I, ST, ID A1 A9 B3 B7 C5 - - - - -
K10 - M5 -
M13 - P5 P6 - -
P13 - R7 R9 - -
C13 - C17 - D1 D3 D6 - - -
R11 - R13 - U8 -
52
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT LED0_1 LED0_2 LED0_3 LED1_1 LED1_2 LED1_3 LED2_1 LED2_2 LED2_3 LED3_1 LED3_2 LED3_3 LED4_1 LED4_2
Ball Type1 P14 - R1 R3 R5 - - -
Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
Signal LED4_3 LED5_1 LED5_2 LED5_3 LED6_1 LED6_2 LED6_3 LED7_1 LED7_2 LED7_3
Ball Type1 J17 J15 J16 H17 H15 H16 G17 G15 F17 F16 E1 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, ID
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 32 (page 90) Table 32 (page 90) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97)
R15 - R17 - T17 - U2 U4 U6 - - -
U10 - U12 - U14 - U16 - U17 - K3 K2 J1 J4 J3 H1 H2 H3 G1 F2 G3 G4 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SO, IP
Table 33 (page 94) MDC0 Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) MDINT1 Table 33 (page 94) MDIO0 Table 33 (page 94) MDIO1 Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) ModeSel0 ModeSel1 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C A10 F3 C9 MDC1 MDDIS MDINT0
B10 I, ST, ID L1 F1 I, ST, ID OD, TS, SL, IP OD, TS, SL, IP I/O, TS, SL, IP I/O, TS, SL, IP
L16 I, ST, ID L17 I, ST, ID F15 - G2 G5 - -
G14 - G16 - H4 -
H14 - J2 J13 K4 - - -
OD, TS, K16 SL, IP K17 OD, TS, SL, IP
K15 -
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
53
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal No ball No ball No ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball
Ball Type1 F6 F7 F8 E8 E10 F9 - - - - -
Reference for Full Description - - - -
Signal No Ball No Ball No Ball No Ball No Ball
Ball Type1 L11 M6 M7 M8 M9 - - - - -
Reference for Full Description - - - - - - - - - - Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
No Ball No Ball No Ball No Ball No Ball PWRDWN REFCLK0 REFCLK1 RESET RxData0_0 RxData0_1 RxData1_0 RxData1_1 RxData2_0 RxData2_1 RxData3_0 RxData3_1 RxData4_0 RxData4_1 RxData5_0 RxData5_1 RxData6_0 RxData6_1 RxData7_0 RxData7_1 RxER0 (MDIX) RxER1 (PAUSE) RxER2 (PREASEL) RxER3 RxER4 (FIFOSEL0)
M10 - M11 - M12 - N8 -
F10 - F11 -
F12 - G6 G7 G8 G9 - - - -
N10 - L14 I, ST, ID E6 I
E12 I M15 I, ST, IP C2 B1 A3 B4 B6 C7 D9 B9 O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID
G10 - G11 - G12 - H5 H6 H7 - - -
H11 - H12 - H13 - J6 J7 J11 J12 K5 K6 K7 - - - - - - -
A13 O, TS C12 O, TS,ID B14 O, TS B15 O, TS, ID C15 O, TS B17 O, TS, ID E16 O, TS F14 O, TS, ID D2 D5 D7 C8 A12 O, TS, SL, ID, I, ST O, TS, SL, ID, I, ST O, TS, SL, ID, I, ST O, TS, SL, ID O, TS, SL, ID, I, ST
K11 - K12 - K13 - L6 L7 L8 L9 - - - -
L10 - L11 -
54
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal RxER5 (FIFOSEL1) RxER6LINK HOLD RxER7 SD_2P5V SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SECTION SGND TCK TDI TDO TMS TPFIN0 TPFIN1 TPFIN2 TPFIN3 TPFIN4 TPFIN5 TPFIN6 TPFIN7 TPFIP0 TPFIP1 TPFIP2 TPFIP3 TPFIP4 TPFIP5 TPFIP6 TPFIP7 TPFON0 TPFON1
Ball Type1 A15 A17 D17 P1 P2 N4 P3 N5 O, TS, SL, ID, I, ST O, TS, SL, ID O, TS, SL, ID I, ST, ID I I I I
Reference for Full Description Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 32 (page 90) Table 34 (page 95) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88)
Signal TPFON2 TPFON3 TPFON4 TPFON5 TPFON6 TPFON7 TPFOP0 TPFOP1 TPFOP2 TPFOP3 TPFOP4 TPFOP5 TPFOP6 TPFOP7 TRST TxData0_0 TxData0_1 TxData1_0 TxData1_1 TxData2_0 TxData2_1 TxData3_0 TxData3_1 TxData4_0 TxData4_1 TxData5_0 TxData5_1 TxData6_0 TxData6_1 TxData7_0 TxData7_1 TxEN0 TxEN1 TxEN2 TxEN3 TxEN4 TxEN5 TxEN6
Ball Type1 U5 T7 AO/AI AO/AI
Reference for Full Description Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 31 (page 89) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
R10 AO/AI U11 AO/AI U15 AO/AI T15 AO/AI T2 T3 T6 U7 AO/AI AO/AI AO/AI AO/AI
P15 I P16 I P17 I N17 I L15 I, ST, ID K14 - M16 I, ST, ID N14 I, ST, IP N15 O, TS N16 I, ST, IP T1 T4 T5 R8 U9 AO/AI AO/AI AO/AI AO/AI AO/AI
T10 AO/AI T11 AO/AI
T14 AO/AI R14 AO/AI M17 I, ST, IP E2 F4 C3 D4 B5 A4 D8 A6 I, ID I, ID I, ID I, ID I, ID I, ID I, ID I, ID
A11 I, ID C10 I, ID B13 I, ID D11 I, ID D13 I, ID A16 I, ID E14 I, ID C16 I, ID E3 B2 C6 A7 I, ID I, ID I, ID I, ID
T12 AO/AI T13 AO/AI T16 AO/AI R2 U3 R6 T8 T9 AO/AI AO/AI AO/AI AO/AI AO/AI
U13 AO/AI R12 AO/AI R16 AO/AI U1 R4 AO/AI AO/AI
B11 I, ID A14 I, ID C14 I, ID
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
55
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal TxEN7 TxSLEW_0 TxSLEW_1 VCCD VCCD VCCD VCCD VCCIO VCCIO VCCIO VCCIO VCCIO VCCPECL VCCPECL VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCT VCCT VCCT VCCT VCCT
Ball Type1 D16 I, ID N3 M4 F5 I, ST, ID I, ST, ID -
Reference for Full Description Table 24 (page 82) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
G13 - J5 J14 A2 A8 C1 - - - - -
C11 - D14 - L5 -
L13 - N13 - P4 P7 P8 P9 - - - -
P10 - P11 - P12 - N6 N7 N9 - - -
N11 - N12 -
56
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 19. Intel(R) LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Signal GNDD VCCIO RxData1_0 TxData2_1 CRS_DV2 TxData3_1 TxEN3 VCCIO GNDD MDIO1 TxData4_0 RxER4 (FIFOSEL0) RxData4_0 TxEN5 RxER5 (FIFOSEL1) TxData6_1 RxER6LINK HOLD RxData0_1 TxEN1 GNDD RxData1_1 TxData2_0 RxData2_0 GNDD CRS_DV3 RxData3_1 MDC1 TxEN4 CRS_DV4 TxData5_0 RxData5_0 RxData5_1 CRS_DV6 Type1 - - O, TS I, ID O, TS, SL I, ID I, ID - - I/O, TS, SL, IP I, ID Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 28 (page 87) C9 Table 24 (page 82) C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 TxData4_1 VCCIO RxData4_1 GNDD TxEN6 RxData6_0 TxData7_1 GNDD GNDD RxER0 (MDIX) GNDD TxData1_1 RxER1 (PAUSE) GNDD RxER2 (PREASEL) TxData3_0 RxData3_0 GNDD TxData5_1 CRS_DV5 TxData6_0 VCCIO GNDD MDINT1 Ball B17 C1 C2 C3 C4 C5 C6 C7 C8 Signal RxData6_1 VCCIO RxData0_0 TxData1_0 CRS_DV1 GNDD TxEN2 RxData2_1 RxER3 Type1 O, TS, ID - O, TS I, ID O, TS, SL - I, ID O, TS, ID Reference for Full Description Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID OD, TS, SL, IP I, ID - O, TS,ID - I, ID O, TS I, ID - - Table 28 (page 87) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95)
O, TS, SL, Table 24 (page 82) ID, I, ST O, TS I, ID Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID, I, ST I, ID Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID O, TS, ID I, ID - O, TS, ID I, ID O, TS - O, TS, SL O, TS, ID I, ST, ID I, ID O, TS, SL I, ID O, TS O, TS, ID O, TS, SL Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 32 (page 90) ID, I, ST - I, ID Table 34 (page 95) Table 24 (page 82)
O, TS, SL, Table 32 (page 90) ID, I, ST - Table 34 (page 95)
O, TS, SL, Table 24 (page 82) ID, I, ST I, ID O, TS - I, ID O, TS, SL I, ID - - Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
57
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball D16 D17 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
Signal TxEN7 RxER7 MDC0 TxData0_0 TxEN0 CRS_DV0 GNDD REFCLK0 GNDD No Ball GNDD No Ball GNDD REFCLK1 GNDD TxData7_0 CRS_DV7 RxData7_0 GNDD MDINT0 LED3_1 MDIO0 TxData0_1 VCCD No ball No ball No ball No Ball No Ball No Ball No Ball GNDD RxData7_1 N/C LED7_3
Type1 I, ID
Reference for Full Description Table 24 (page 82)
Ball F17 G1 G2 G3 G4 G5 G6 G7 G8 G9
Signal LED7_2 LED2_3 N/C LED3_2 LED3_3 N/C No Ball No Ball No Ball No Ball No Ball No Ball No Ball VCCD N/C LED7_1 N/C LED6_3 LED1_3 LED2_1 LED2_2 N/C No Ball No Ball No Ball GNDD GNDD GNDD No Ball No Ball No Ball N/C
Type1 OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SO, IP - - - - - - - - - - OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - - - - - - - - - -
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - - - - - Table 34 (page 95) Table 35 (page 97) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - - Table 35 (page 97)
O, TS, SL, Table 24 (page 82) ID I, ST, ID I, ID I, ID O, TS, SL - I - - - Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) - Table 34 (page 95)
- I - I, ID O, TS, SL O, TS - OD, TS, SL, IP OD, TS, SL, IP I/O, TS, SL, IP I, ID - - - - - - - - - O, TS, ID - OD, TS, SL, IP
Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 28 (page 87) Table 33 (page 94) Table 28 (page 87) Table 24 (page 82) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 24 (page 82) Table 35 (page 97) Table 33 (page 94)
G10 G11 G12 G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14
58
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball H15 H16 H17 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
Signal LED6_1 LED6_2 LED5_3 LED0_3 N/C LED1_2 LED1_1 VCCD No Ball No Ball GNDD GNDD GNDD No Ball No Ball N/C VCCD LED5_1 LED5_2 LED4_3 AMDIX_EN LED0_2 LED0_1 N/C No Ball No Ball No Ball GNDD GNDD GNDD No Ball
Type1 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP - - - - - - - - - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP OD, TS, SL, IP OD, TS, SL, IP - - - - - - - -
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 34 (page 95) - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - Table 35 (page 97) Table 34 (page 95) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 32 (page 90) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) -
Ball K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L11 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14
Signal No Ball No Ball SGND N/C LED4_1 LED4_2 MDDIS CFG_3 CFG_2 ADD_4 VCCPECL No Ball No Ball No Ball No Ball No Ball No Ball No Ball VCCPECL PWRDWN SECTION ModeSel0 ModeSel1 CFG_1 ADD_3 ADD_2 TxSLEW_1 GNDPECL No Ball No Ball No Ball No Ball No Ball No Ball No Ball GNDPECL G_FX/TP
Type1 - - - - OD, TS, SL, IP OD, TS, SL, IP I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID
Reference for Full Description - - Table 34 (page 95) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
59
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1
Signal RESET TCK TRST ADD_1 ADD_0 TxSLEW_0 SD1 SD3 VCCT VCCT No Ball VCCT No Ball VCCT VCCT VCCR TDI TDO TMS SD7 SD_2P5V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR VCCR VCCR VCCR GNDR GNDT SD4 SD5 SD6 GNDT
Type1 I, ST, IP I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID I I - - - - - - - - I, ST, IP O, TS I, ST, IP I I, ST, ID I I - - - - - - - - - - - I I I -
Reference for Full Description Table 32 (page 90) Table 31 (page 89) Table 31 (page 89) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) - Table 34 (page 95) - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95)
Ball R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5
Signal TPFIP0 GNDT TPFON1 GNDT TPFIP2 GNDR TPFIN3 GNDR TPFON4 GNDR TPFIP6 GNDR TPFOP7 GNDT TPFIP7 GNDT TPFIN0 TPFOP0 TPFOP1 TPFIN1 TPFIN2 TPFOP2 TPFON3 TPFIP3 TPFIP4 TPFOP4 TPFOP5 TPFIN5 TPFIN6 TPFOP6 TPFON7 TPFIN7 GNDT TPFON0 GNDT TPFIP1 GNDT TPFON2
Type1 AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI - AO/AI - AO/AI - AO/AI
Reference for Full Description Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88)
60
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Signal GNDT TPFOP3 GNDR TPFIN4 GNDT TPFON5 GNDT TPFIP5 GNDT TPFON6 GNDT GNDT
Type1 - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - -
Reference for Full Description Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 34 (page 95)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
61
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.2
SMII BGA23 Ball List
The following tables provide the SMII ball locations and signal names arranged in alphanumeric order as follows:
* Table 20 "Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by
Signal Name"
* Table 21 "Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball
Location" on page 67 Table 20. Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Signal Name
Signal ADD_0 ADD_1 ADD_2 ADD_3 ADD_4 AMDIX_EN CFG_1 CFG_2 CFG_3 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 FIFOSEL0 FIFOSEL1 G_FX/TP GNDD GNDD GNDD GNDD GNDD GNDD GNDD Ball Type1 N2 N1 M3 M2 L4 K1 M1 L3 L2 E4 C4 A5 B8 I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID O, TS, SL O, TS, SL O, TS, SL O, TS, SL Reference for Full Description Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Signal GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDPECL GNDPECL GNDR GNDR GNDR GNDR GNDR Ball Type1 D1 D3 D6 - - - Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
D10 - D15 - E5 E7 E9 - - -
E11 - E13 - E17 - F13 - H8 H9 - -
B12 O, TS, SL D12 O, TS, SL B16 O, TS, SL E15 O, TS, SL
H10 - J8 J9 J10 K8 K9 - - - - -
O, TS, SL, A12 Table 24 (page 82) ID, I, ST A15 O, TS, SL, Table 24 (page 82) ID, I, ST Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
M14 I, ST, ID A1 A9 B3 B7 C5 - - - - -
K10 - M5 -
M13 - P5 P6 - -
P13 - R7 R9 - -
C13 - C17 -
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Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal GNDR GNDR GNDR GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT LED0_1 LED0_2 LED0_3 LED1_1 LED1_2 LED1_3 LED2_1 LED2_2 LED2_3 LED3_1 LED3_2 LED3_3
Ball Type1 R11 - R13 - U8 -
Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94)
Signal LED4_1 LED4_2 LED4_3 LED5_1 LED5_2 LED5_3 LED6_1 LED6_2 LED6_3 LED7_1 LED7_2 LED7_3 LINKHOLD MDC0 MDC1 MDDIS MDINT0 MDINT1
Ball Type1 K16 K17 J17 J15 J16 H17 H15 H16 G17 G15 F17 F16 A17 E1 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94)
P14 - R1 R3 R5 - - -
R15 - R17 - T17 - U2 U4 U6 - - -
U10 - U12 - U14 - U16 - U17 - K3 K2 J1 J4 J3 H1 H2 H3 G1 F2 G3 G4 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SO, IP
O, TS, SL, Table 24 (page 82) ID, I, ST I, ST, ID Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87) Table 28 (page 87)
B10 I, ST, ID L1 F1 C9 F3 A10 D2 I, ST, ID OD, TS, SL, IP OD, TS, SL, IP I/O, TS, SL, IP I/O, TS, SL, IP
Table 33 (page 94) MDIO0 Table 33 (page 94) MDIO1 Table 33 (page 94) MDIX Table 33 (page 94) ModeSel0 Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) ModeSel1 N/C N/C N/C N/C
O, TS, SL, Table 32 (page 90) ID, I, ST Table 32 (page 90) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
L16 I, ST, ID L17 I, ST, ID A4 A7 I, ID I, ID
A14 I, ID A16 I, ID
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
63
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C No ball No ball No ball No Ball No Ball No Ball
Ball Type1 B1 B2 B4 B9 O, TS, ID I, ID O, TS, ID O, TS, ID
Reference for Full Description Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
Signal No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball
Ball Type1 F10 - F11 -
Reference for Full Description - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
F12 - G6 G7 G8 G9 - - - -
B11 I, ID B15 O, TS, ID B17 O, TS, ID C6 C7 C8 I, ID O, TS, ID
G10 - G11 - G12 - H5 H6 H7 - - -
O, TS, SL, Table 24 (page 82) ID Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
C10 I, ID C12 O, TS,ID C14 I, ID D4 I, ID
H11 - H12 - H13 - J6 J7 J11 J12 K5 K6 K7 - - - - - - -
D11 I, ID D16 I, ID
O, TS, SL, D17 Table 24 (page 82) ID E3 F4 I, ID I, ID Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) - - - -
F14 O, TS, ID F15 - G2 G5 - -
K11 - K12 - K13 - L6 L7 L8 L9 - - - -
G14 - G16 - H4 -
H14 - J2 J13 K4 - - -
L10 - L11 L11 M6 M7 M8 M9 - - - - - -
K15 - F6 F7 F8 E8 E10 F9 - - - - -
-
No Ball
M10 -
64
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal No Ball No Ball No Ball No Ball PAUSE PREASEL PWRDWN REFCLK0 REFCLK1 RESET RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7 SD_2P5V SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SECTION SGND SYNC0 SYNC1 TCK TDI TDO TMS TPFIN0 TPFIN1
Ball Type1 M11 - M12 - N8 -
Reference for Full Description - - - -
Signal TPFIN2 TPFIN3 TPFIN4 TPFIN5 TPFIN6 TPFIN7 TPFIP0 TPFIP1 TPFIP2 TPFIP3 TPFIP4 TPFIP5 TPFIP6 TPFIP7 TPFON0 TPFON1 TPFON2 TPFON3 TPFON4 TPFON5 TPFON6 TPFON7 TPFOP0 TPFOP1 TPFOP2 TPFOP3 TPFOP4 TPFOP5 TPFOP6 TPFOP7 TRST TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6
Ball Type1 T5 R8 U9 AO/AI AO/AI AO/AI
Reference for Full Description Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 31 (page 89) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
N10 - D5 D7
T12 AO/AI T13 AO/AI T16 AO/AI R2 U3 R6 T8 T9 AO/AI AO/AI AO/AI AO/AI AO/AI
O, TS, SL, Table 32 (page 90) ID, I, ST O, TS, SL, Table 24 (page 82) ID, I, ST Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 32 (page 90) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 30 (page 88) Table 30 (page 88)
L14 I, ST, ID E6 I
E12 I M15 I, ST, IP C2 A3 B6 D9 O, TS O, TS O, TS O, TS
U13 AO/AI R12 AO/AI R16 AO/AI U1 R4 U5 T7 AO/AI AO/AI AO/AI AO/AI
A13 O, TS B14 O, TS C15 O, TS E16 O, TS P1 P2 N4 P3 N5 I, ST, ID I I I I
R10 AO/AI U11 AO/AI U15 AO/AI T15 AO/AI T2 T3 T6 U7 AO/AI AO/AI AO/AI AO/AI
P15 I P16 I P17 I N17 I L15 I, ST, ID K14 - A6 I, ID
T10 AO/AI T11 AO/AI
T14 AO/AI R14 AO/AI M17 I, ST, IP E2 C3 B5 D8 I, ID I, ID I, ID I, ID
C16 I, ID M16 I, ST, ID N14 I, ST, IP N15 O, TS N16 I, ST, IP T1 T4 AO/AI AO/AI
A11 I, ID B13 I, ID D13 I, ID
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
65
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal TxData7 TxSLEW_0 TxSLEW_1 VCCD VCCD VCCD VCCD VCCIO VCCIO VCCIO VCCIO VCCIO VCCPECL VCCPECL VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCT VCCT VCCT VCCT VCCT
Ball Type1 E14 I, ID N3 M4 F5 I, ST, ID I, ST, ID -
Reference for Full Description Table 24 (page 82) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
G13 - J5 J14 A2 A8 C1 - - - - -
C11 - D14 - L5 -
L13 - N13 - P4 P7 P8 P9 - - - -
P10 - P11 - P12 - N6 N7 N9 - - -
N11 - N12 -
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 21. Intel(R) LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location
Ball Signal A1 A2 A3 A4 A5 A6 A7 A8 A9 GNDD VCCIO RxData1 N/C CRS_DV2 SYNC0 N/C VCCIO GNDD Type1 - - O, TS I, ID O, TS, SL I, ID I, ID - - Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Ball Signal B17 N/C C1 C2 C3 C4 C5 C6 C7 C8 C9 VCCIO RxData0 TxData1 CRS_DV1 GNDD N/C N/C N/C MDINT1 Type1 O, TS, ID - O, TS I, ID O, TS, SL - I, ID O, TS, ID O, TS, SL, ID Reference for Full Description Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
A10 MDIO1 A11 TxData4 A12 FIFOSEL0 A13 RxData4 A14 N/C A15 FIFOSEL1 A16 N/C A17 LINKHOLD B1 B2 B3 B4 B5 B6 B7 B8 B9 N/C N/C GNDD N/C TxData2 RxData2 GNDD CRS_DV3 N/C
I/O, TS, SL, Table 28 (page 87) IP I, ID O, TS, SL, ID, I, ST O, TS I, ID O, TS, SL, ID, I, ST I, ID O, TS, SL, ID O, TS - - O, TS, ID I, ID O, TS - O, TS, SL O, TS, ID I, ST, ID I, ID O, TS, SL I, ID O, TS O, TS, ID O, TS, SL Table 24 (page 82)
OD, TS, SL, Table 28 (page 87) IP I, ID - O, TS,ID - I, ID O, TS I, ID - - O, TS, SL, ID, I, ST - I, ID O, TS, SL, ID, I, ST - O, TS, SL, ID, I, ST I, ID O, TS - I, ID O, TS, SL I, ID - - Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 32 (page 90) Table 34 (page 95) Table 24 (page 82) Table 32 (page 90) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95)
C10 N/C Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) D8 D9 TxData3 RxData3 D5 D6 D7 PAUSE GNDD PREASEL C11 VCCIO C12 N/C C13 GNDD C14 N/C C15 RxData6 C16 SYNC1 C17 GNDD D1 D2 D3 D4 GNDD MDIX GNDD N/C
B10 MDC1 B11 N/C B12 CRS_DV4 B13 TxData5 B14 RxData5 B15 N/C B16 CRS_DV6
D10 GNDD D11 N/C D12 CRS_DV5 D13 TxData6 D14 VCCIO D15 GNDD
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal D16 N/C D17 N/C E1 E2 E3 E4 E5 E6 E7 E8 E9 MDC0 TxData0 N/C CRS_DV0 GNDD REFCLK0 GNDD No Ball GNDD
Type1 I, ID O, TS, SL, ID I, ST, ID I, ID I, ID O, TS, SL - I - - -
Reference for Full Description Table 24 (page 82) Table 24 (page 82)
Ball Signal F17 LED7_2 G1 LED2_3 N/C LED3_2 LED3_3 N/C No Ball No Ball No Ball No Ball
Type1
Reference for Full Description
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP - Table 35 (page 97)
Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) - Table 34 (page 95) G2 G3 G4 G5 G6 G7 G8 G9
OD, TS, SL, Table 33 (page 94) IP OD, TS, SO, IP - - - - - - - - - - Table 33 (page 94) Table 35 (page 97) - - - - - - - Table 34 (page 95) Table 35 (page 97)
E10 No Ball E11 GNDD E12 REFCLK1 E13 GNDD E14 TxData7 E15 CRS_DV7 E16 RxData7 E17 GNDD F1 F2 F3 F4 F5 F6 F7 F8 F9 MDINT0 LED3_1 MDIO0 N/C VCCD No ball No ball No ball No Ball - I - I, ID O, TS, SL O, TS - Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95)
G10 No Ball G11 No Ball G12 No Ball G13 VCCD G14 N/C G15 LED7_1 G16 N/C G17 LED6_3 H1 H2 H3 H4 H5 H6 H7 H8 H9 LED1_3 LED2_1 LED2_2 N/C No Ball No Ball No Ball GNDD GNDD
OD, TS, SL, Table 33 (page 94) IP - Table 35 (page 97)
OD, TS, SL, Table 28 (page 87) IP OD, TS, SL, Table 33 (page 94) IP I/O, TS, SL, Table 28 (page 87) IP I, ID - - - - - - - - - O, TS, ID - Table 24 (page 82) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 24 (page 82) Table 35 (page 97)
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP - - - - - - - - - - - Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - - Table 35 (page 97)
F10 No Ball F11 No Ball
F12 No Ball F13 GNDD F14 N/C F15 N/C F16 LED7_3
H10 GNDD H11 No Ball H12 No Ball H13 No Ball H14 N/C
OD, TS, SL, Table 33 (page 94) IP
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal H15 LED6_1 H16 LED6_2 H17 LED5_3 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 LED0_3 N/C LED1_2 LED1_1 VCCD No Ball No Ball GNDD GNDD GNDD No Ball No Ball N/C VCCD LED5_1 LED5_2 LED4_3 AMDIX_EN LED0_2 LED0_1 N/C No Ball No Ball No Ball GNDD GNDD
Type1
Reference for Full Description
Ball Signal K12 No Ball K13 No Ball K14 SGND K15 N/C K16 LED4_1 K17 LED4_2 L1 L2 L3 L4 L5 L6 L7 L8 L9 MDDIS CFG_3 CFG_2 ADD_4 VCCPECL No Ball No Ball No Ball No Ball
Type1 - - - -
Reference for Full Description - - Table 34 (page 95) Table 35 (page 97)
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP - Table 35 (page 97)
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID Table 28 (page 87) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90)
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP - - - - - - - - - - Table 34 (page 95) - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - Table 35 (page 97) Table 34 (page 95)
L10 No Ball L11 L11 No Ball No Ball
L13 VCCPECL L14 PWRDWN L15 SECTION L16 ModeSel0 L17 ModeSel1 M1 M2 M3 M4 M5 M6 M7 M8 M9 CFG_1 ADD_3 ADD_2 TxSLEW_1 GNDPECL No Ball No Ball No Ball No Ball
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP I, ST, IP Table 32 (page 90)
OD, TS, SL, Table 33 (page 94) IP OD, TS, SL, Table 33 (page 94) IP - - - - - - - - Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) -
M10 No Ball M11 No Ball M12 No Ball M13 GNDPECL M14 G_FX/TP
K10 GNDD K11 No Ball
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
69
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal M15 RESET M16 TCK M17 TRST N1 N2 N3 N4 N5 N6 N7 N8 N9 ADD_1 ADD_0 TxSLEW_0 SD1 SD3 VCCT VCCT No Ball VCCT
Type1 I, ST, IP I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID I I - - - - - - - - I, ST, IP O, TS I, ST, IP I I, ST, ID I I - - - - - - - - - - - I I I -
Reference for Full Description Table 32 (page 90) Table 31 (page 89) Table 31 (page 89) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) - Table 34 (page 95) - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95)
Ball Signal R2 R3 R4 R5 R6 R7 R8 R9 TPFIP0 GNDT TPFON1 GNDT TPFIP2 GNDR TPFIN3 GNDR
Type1 AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI - AO/AI - AO/AI - AO/AI
Reference for Full Description Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88)
R10 TPFON4 R11 GNDR R12 TPFIP6 R13 GNDR R14 TPFOP7 R15 GNDT R16 TPFIP7 R17 GNDT T1 T2 T3 T4 T5 T6 T7 T8 T9 TPFIN0 TPFOP0 TPFOP1 TPFIN1 TPFIN2 TPFOP2 TPFON3 TPFIP3 TPFIP4
N10 No Ball N11 VCCT N12 VCCT N13 VCCR N14 TDI N15 TDO N16 TMS N17 SD7 P1 P2 P3 P4 P5 P6 P7 P8 P9 SD_2P5V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR
T10 TPFOP4 T11 TPFOP5
T12 TPFIN5 T13 TPFIN6 T14 TPFOP6 T15 TPFON7 T16 TPFIN7 T17 GNDT U1 U2 U3 U4 U5 TPFON0 GNDT TPFIP1 GNDT TPFON2
P10 VCCR P11 VCCR P12 VCCR P13 GNDR P14 GNDT P15 SD4 P16 SD5 P17 SD6 R1 GNDT
70
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Signal U6 U7 U8 U9 GNDT TPFOP3 GNDR TPFIN4
Type1 - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - -
Reference for Full Description Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 34 (page 95)
U10 GNDT U11 TPFON5 U12 GNDT U13 TPFIP5 U14 GNDT U15 TPFON6 U16 GNDT U17 GNDT
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.3.3
SS-SMII BGA23 Ball List
The following tables provide the SS-SMII ball locations and signal names arranged in alphanumeric order as follows:
* Table 22 "Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Signal Name"
* Table 23 "Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by
Ball Location" on page 77 Table 22. Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Signal Name
Signal ADD_0 ADD_1 ADD_2 ADD_3 ADD_4 AMDIX_EN CFG_1 CFG_2 CFG_3 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 FIFOSEL0 FIFOSEL1 G_FX/TP GNDD GNDD GNDD GNDD GNDD GNDD Ball Type1 N2 N1 M3 M2 L4 K1 M1 L3 L2 E4 C4 A5 B8 I I, ST, ID - - - - - - - OD, TS, SL, IP - I, ST, ID - Reference for Full Description Table 29 (page 88) Table 29 (page 88) - - - - - - - Table 33 (page 94) Table 34 (page 95) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 33 (page 94) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDPECL GNDPECL GNDR E17 GNDD GNDD GNDD GNDD E7 E9 E11 E13 Signal GNDD GNDD GNDD GNDD GNDD GNDD GNDD Ball Type1 C17 - D1 D3 D6 - - - Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) - - - - - - Table 32 (page 90) Table 24 (page 82) Table 30 (page 88)
D10 - D15 - E5 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
B12 - D12 - B16 - E15 A12 A15 OD, TS, SO, IP O, TS, SL, I, ST O, TS, SL, I, ST
F13 I, ST, ID H8 H9 - I, ID
H10 I, ID J8 J9 J10 K8 K9 - - - - -
M14 O, TS A1 A9 B3 B7 C5 I, ST, ID I, ST, ID - - -
K10 - M5 I, ST, ID
M13 O, TS P5 AO/AI
C13 -
72
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal GNDR GNDR GNDR GNDR GNDR GNDR GNDR GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT GNDT LED0_1 LED0_2 LED0_3 LED1_1 LED1_2 LED1_3 LED2_1 LED2_2 LED2_3 LED3_1 LED3_2 LED3_3 LED4_1 LED4_2
Ball Type1 P6 AO/AI
Reference for Full Description Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88)
Signal LED4_3 LED5_1 LED5_2 LED5_3 LED6_1 LED6_2 LED6_3 LED7_1 LED7_2 LED7_3 LINKHOLD MDC0 MDC1 MDDIS MDINT0 MDINT1 MDIO0 MDIO1 MDIX ModeSel0 ModeSel1 N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C
Ball Type1 J17 J15 J16 - - -
Reference for Full Description - - - Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 24 (page 82) Table 24 (page 82) Table 28 (page 87) Table 28 (page 87) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) - Table 33 (page 94) Table 34 (page 95) Table 33 (page 94) Table 24 (page 82) Table 34 (page 95) - - Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
P13 AO/AI R7 R9 AO/AI AO/AI
H17 - H15 - H16 - G17 - G15 I, ID I/O, TS, F17 SL, IP F16 I/O, TS, SL, IP
R11 AO/AI R13 AO/AI U8 -
P14 AO/AI R1 R3 R5 R15 AO/AI AO/AI AO/AI
O, TS, SL, Table 24 (page 82) ID Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - Table 35 (page 97) Table 35 (page 97) Table 35 (page 97) Table 24 (page 82)
A17 O, TS, SL E1 -
R17 I, ID T17 - U2 U4 U6 - - -
B10 - L1 F1 C9 F3 - OD, TS, SL, IP - OD, TS, SL, IP
U10 - U12 - U14 - U16 - U17 - K3 K2 J1 J4 J3 H1 H2 H3 G1 F2 G3 G4 - - - - - I, ID
A10 O, TS, SL D2 I, ST
L16 - L17 - A3 A4 A7 I, ST, ID I, ST, ID I, ST, ID
A13 O, TS, SL A14 O, TS, SL A16 O, TS, SL B2 B6 - -
O, TS, SL, Table 24 (page 82) ID I, ID Table 24 (page 82)
O, TS, SL, Table 32 (page 90) ID OD, TS, SL, IP I, ST, ID - Table 33 (page 94) Table 32 (page 90) Table 24 (page 82) - -
B11 - B14 - C2 C6 C8 - - -
N/C N/C N/C N/C N/C
K16 - K17 -
C10 - C14 -
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
73
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C No ball No ball No ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball
Ball Type1 C15 - D4 D9 - -
Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 35 (page 97) Table 35 (page 97) - - - Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
Signal No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball PAUSE
Ball Type1 G10
Reference for Full Description
O, TS, SL, Table 24 (page 82) ID Table 24 (page 82)
G11 I, ID G12 H5 H6 H7
D11 - D16 - OD, TS, E16 SL, IP F4 F15 G2 G5 OD, TS, SL, IP OD, TS, SL, IP I, ST, ID I, ID
O, TS, SL, Table 24 (page 82) ID - I, ID Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID Table 24 (page 82) Table 24 (page 82) Table 35 (page 97) Table 35 (page 97) -
H11 - H12 I, ID H13 - J6 J7 J11 J12 K5 K6 K7 - - - - - -
G14 - G16 - H4 I, ID
- - - - - - - - - - - - - - Table 24 (page 82) Table 24 (page 82) Table 32 (page 90) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 29 (page 88) Table 32 (page 90) Table 34 (page 95)
H14 - J2 J13 K4 - - -
K11 - K12 - K13 - L6 L7 L8 L9 - - - -
K15 - F6 F7 F8 E8 E10 F9 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
L10 - L11 L11 M6 M7 M8 M9 - - I I I, ST, IP I, ID
OD, TS, F10 SL, IP F11 I, ST, ID
F12 I, ST, ID G6 G7 G8 G9 I, ID O, TS, SL, ID - I, ID
M10 O, TS M11 O, TS M12 O, TS N8 I
N10 I, ST, ID D5 I, ST
74
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal PREASEL PWRDWN REFCLK0 REFCLK1 RESET RxCLK0 RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7 SD_2P5V SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SECTION SGND TCK TDI TDO TMS TPFIN0 TPFIN1 TPFIN2 TPFIN3 TPFIN4 TPFIN5 TPFIN6
Ball Type1 D7 I, ST
Reference for Full Description Table 34 (page 95) - Table 33 (page 94) Table 33 (page 94) Table 24 (page 82) Table 34 (page 95) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 28 (page 87) Table 30 (page 88) Table 30 (page 88) Table 29 (page 88) Table 30 (page 88) Table 29 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) - - Table 24 (page 82) Table 31 (page 89) Table 31 (page 89) Table 30 (page 88) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 30 (page 88) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95)
Signal TPFIN7 TPFIP0 TPFIP1 TPFIP2 TPFIP3 TPFIP4 TPFIP5 TPFIP6 TPFIP7 TPFON0 TPFON1 TPFON2 TPFON3 TPFON4 TPFON5 TPFON6 TPFON7 TPFOP0 TPFOP1 TPFOP2 TPFOP3 TPFOP4 TPFOP5 TPFOP6 TPFOP7 TRST TxCLK1 TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 TxSLEW_0 TxSLEW_1
Ball Type1 T16 - R2 U3 R6 T8 T9 AO/AI - AO/AI I, ST, ID I, ID
Reference for Full Description Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 32 (page 90) Table 24 (page 82) Table 34 (page 95) Table 30 (page 88) Table 24 (page 82) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 32 (page 90) Table 30 (page 88) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 31 (page 89) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 33 (page 94) Table 29 (page 88)
L14 - E6 E12 OD, TS, SL, IP OD, TS, SL, IP
M15 O, TS, ID E3 B1 B4 C7 B9 - I, ST, ID - - -
U13 - R12 AO/AI R16 I, ID U1 R4 U5 T7 - AO/AI - I, ST, ID
C12 - B15 - B17 - F14 P1 P2 N4 P3 N5 OD, TS, SL, IP AO/AI AO/AI I AO/AI I
R10 AO/AI U11 - U15 - T15 - T2 T3 T6 U7 I, ID I, ID I, ID -
P15 AO/AI P16 AO/AI P17 AO/AI N17 AO/AI L15 - K14 - M16 O, TS, ID N14 O, TS N15 I, ST, IP N16 AO/AI T1 T4 T5 R8 U9 I, ID I, ID I, ID AO/AI -
T10 I, ID T11 -
T14 - R14 I, ST, IP M17 O, TS, ID D17 - E2 C3 B5 D8 - - - -
A11 O, TS, SL B13 - D13 - E14 N3 M4 OD, TS, SL, IP I
T12 - T13 -
O, TS, SL, Table 32 (page 90) ID
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
75
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal TxSYNC0 TxSYNC1 VCCD VCCD VCCD VCCD VCCIO VCCIO VCCIO VCCIO VCCIO VCCPECL VCCPECL VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCR VCCT VCCT VCCT VCCT VCCT
Ball Type1 A6 I, ST, IP
Reference for Full Description Table 32 (page 90) Table 34 (page 95) Table 33 (page 94) Table 24 (page 82) Table 35 (page 97) - Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - Table 31 (page 89) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 31 (page 89)
C16 - F5 OD, TS, SL, IP
G13 I, ID J5 J14 A2 A8 C1 - - I, ST, ID I, ST, ID -
C11 - D14 - L5 -
L13 - N13 I, ST, IP P4 P7 P8 P9 AO/AI AO/AI AO/AI AO/AI
P10 AO/AI P11 AO/AI P12 AO/AI N6 N7 N9 I I I
N11 - N12 I, ST, ID
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 23. Intel(R) LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location
Ball Symbol A1 A2 A3 A4 A5 A6 A7 A8 A9 GNDD VCCIO N/C N/C CRS_DV2 TxSYNC0 N/C VCCIO GNDD Type1 - - O, TS I, ID O, TS, SL I, ID I, ID - - I/O, TS, SL, IP I, ID Reference for Full Description Table 34 (page 95) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95) Table 28 (page 87) C9 Table 24 (page 82) C10 N/C C11 VCCIO C12 RxData4 C13 GNDD C14 N/C C15 N/C C16 TxSYNC1 C17 GNDD D1 D2 D3 D4 D5 D6 D7 D8 D9 GNDD MDIX GNDD N/C PAUSE GNDD PREASEL TxData3 N/C MDINT1 Ball Symbol B17 RxData6 C1 C2 C3 C4 C5 C6 C7 C8 VCCIO N/C TxData1 CRS_DV1 GNDD N/C RxData2 N/C Type1 O, TS, ID - - I, ID O, TS, SL - I, ID O, TS, ID Reference for Full Description Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID OD, TS, SL, IP I, ID - O, TS,ID - I, ID O, TS I, ID - - Table 28 (page 87) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95)
A10 MDIO1 A11 TxData4 A12 FIFOSEL0 A13 N/C A14 N/C A15 FIFOSEL1 A16 N/C A17 LINKHOLD B1 B2 B3 B4 B5 B6 B7 B8 B9 RxData0 N/C GNDD RxData1 TxData2 N/C GNDD CRS_DV3 RxData3
O, TS, SL, Table 24 (page 82) ID, I, ST O, TS I, ID Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID, I, ST I, ID Table 24 (page 82)
O, TS, SL, Table 24 (page 82) ID, I, ST O, TS I, ID - O, TS, ID I, ID O, TS - O, TS, SL O, TS, ID I, ST, ID I, ID O, TS, SL I, ID O, TS O, TS, ID O, TS, SL Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82)
O, TS, SL, Table 32 (page 90) ID, I, ST - I, ID Table 34 (page 95) Table 24 (page 82)
O, TS, SL, Table 32 (page 90) ID, I, ST - Table 34 (page 95)
O, TS, SL, Table 24 (page 82) ID, I, ST I, ID O, TS - I, ID O, TS, SL I, ID - - Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 34 (page 95)
B10 MDC1 B11 N/C B12 CRS_DV4 B13 TxData5 B14 N/C B15 RxData5 B16 CRS_DV6
D10 GNDD D11 N/C D12 CRS_DV5 D13 TxData6 D14 VCCIO D15 GNDD
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
77
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol D16 N/C D17 TxCLK1 E1 E2 E3 E4 E5 E6 E7 E8 E9 MDC0 TxData0 RxCLK0 CRS_DV0 GNDD REFCLK0 GNDD No Ball GNDD
Type1 I, ID O, TS, SL, ID I, ST, ID I, ID I, ID O, TS, SL - I - - -
Reference for Full Description Table 24 (page 82) Table 24 (page 82)
Ball Symbol F17 LED7_2 G1 LED2_3 N/C LED3_2 LED3_3 N/C No Ball No Ball No Ball No Ball
Type1 OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SO, IP - - - - - - - - - - OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - - - - - - - - - - -
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - - - - - Table 34 (page 95) Table 35 (page 97) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - - Table 35 (page 97)
Table 28 (page 87) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) - Table 34 (page 95) G2 G3 G4 G5 G6 G7 G8 G9
E10 No Ball E11 GNDD E12 REFCLK1 E13 GNDD E14 TxData7 E15 CRS_DV7 E16 N/C E17 GNDD F1 F2 F3 F4 F5 F6 F7 F8 F9 MDINT0 LED3_1 MDIO0 N/C VCCD No ball No ball No ball No Ball - I - I, ID O, TS, SL O, TS - OD, TS, SL, IP OD, TS, SL, IP I/O, TS, SL, IP I, ID - - - - - - - - - O, TS, ID - OD, TS, SL, IP Table 34 (page 95) Table 24 (page 82) Table 34 (page 95) Table 24 (page 82) Table 24 (page 82) Table 24 (page 82) Table 34 (page 95) Table 28 (page 87) Table 33 (page 94) Table 28 (page 87) Table 24 (page 82) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 24 (page 82) Table 35 (page 97) Table 33 (page 94)
G10 No Ball G11 No Ball G12 No Ball G13 VCCD G14 N/C G15 LED7_1 G16 N/C G17 LED6_3 H1 H2 H3 H4 H5 H6 H7 H8 H9 LED1_3 LED2_1 LED2_2 N/C No Ball No Ball No Ball GNDD GNDD
F10 No Ball F11 No Ball
F12 No Ball F13 GNDD F14 RxData7 F15 N/C F16 LED7_3
H10 GNDD H11 No Ball H12 No Ball H13 No Ball H14 N/C
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol H15 LED6_1 H16 LED6_2 H17 LED5_3 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 LED0_3 N/C LED1_2 LED1_1 VCCD No Ball No Ball GNDD GNDD GNDD No Ball No Ball N/C VCCD LED5_1 LED5_2 LED4_3 AMDIX_EN LED0_2 LED0_1 N/C No Ball No Ball No Ball GNDD GNDD
Type1 OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - OD, TS, SL, IP OD, TS, SL, IP - - - - - - - - - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP OD, TS, SL, IP OD, TS, SL, IP - - - - - - - -
Reference for Full Description Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 34 (page 95) - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) - - Table 35 (page 97) Table 34 (page 95) Table 33 (page 94) Table 33 (page 94) Table 33 (page 94) Table 32 (page 90) Table 33 (page 94) Table 33 (page 94) Table 35 (page 97) - - - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) -
Ball Symbol K12 No Ball K13 No Ball K14 SGND K15 N/C K16 LED4_1 K17 LED4_2 L1 L2 L3 L4 L5 L6 L7 L8 L9 MDDIS CFG_3 CFG_2 ADD_4 VCCPECL No Ball No Ball No Ball No Ball
Type1 - - - - OD, TS, SL, IP OD, TS, SL, IP I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID I, ST, ID - - - - - - - - - I, ST, ID
Reference for Full Description - - Table 34 (page 95) Table 35 (page 97) Table 33 (page 94) Table 33 (page 94) Table 28 (page 87) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 34 (page 95) - - - - - - - Table 34 (page 95) Table 32 (page 90)
L10 No Ball L11 L11 No Ball No Ball
L13 VCCPECL L14 PWRDWN L15 SECTION L16 ModeSel0 L17 ModeSel1 M1 M2 M3 M4 M5 M6 M7 M8 M9 CFG_1 ADD_3 ADD_2 TxSLEW_1 GNDPECL No Ball No Ball No Ball No Ball
M10 No Ball M11 No Ball M12 No Ball M13 GNDPECL M14 G_FX/TP
K10 GNDD K11 No Ball
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol M15 RESET M16 TCK M17 TRST N1 N2 N3 N4 N5 N6 N7 N8 N9 ADD_1 ADD_0 TxSLEW_0 SD1 SD3 VCCT VCCT No Ball VCCT
Type1 I, ST, IP I, ST, ID I, ST, IP I, ST, ID I, ST, ID I, ST, ID I I - - - - - - - - I, ST, IP O, TS I, ST, IP I I, ST, ID I I - - - - - - - - - - - I I I -
Reference for Full Description Table 32 (page 90) Table 31 (page 89) Table 31 (page 89) Table 32 (page 90) Table 32 (page 90) Table 32 (page 90) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) - Table 34 (page 95) - Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 31 (page 89) Table 31 (page 89) Table 31 (page 89) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 34 (page 95) Table 29 (page 88) Table 29 (page 88) Table 29 (page 88) Table 34 (page 95)
Ball Symbol R2 R3 R4 R5 R6 R7 R8 R9 TPFIP0 GNDT TPFON1 GNDT TPFIP2 GNDR TPFIN3 GNDR
Type1 AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI - AO/AI - AO/AI - AO/AI
Reference for Full Description Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88)
R10 TPFON4 R11 GNDR R12 TPFIP6 R13 GNDR R14 TPFOP7 R15 GNDT R16 TPFIP7 R17 GNDT T1 T2 T3 T4 T5 T6 T7 T8 T9 TPFIN0 TPFOP0 TPFOP1 TPFIN1 TPFIN2 TPFOP2 TPFON3 TPFIP3 TPFIP4
N10 No Ball N11 VCCT N12 VCCT N13 VCCR N14 TDI N15 TDO N16 TMS N17 SD7 P1 P2 P3 P4 P5 P6 P7 P8 P9 SD_2P5V SD0 SD2 VCCR GNDR GNDR VCCR VCCR VCCR
T10 TPFOP4 T11 TPFOP5
T12 TPFIN5 T13 TPFIN6 T14 TPFOP6 T15 TPFON7 T16 TPFIN7 T17 GNDT U1 U2 U3 U4 U5 TPFON0 GNDT TPFIP1 GNDT TPFON2
P10 VCCR P11 VCCR P12 VCCR P13 GNDR P14 GNDT P15 SD4 P16 SD5 P17 SD6 R1 GNDT
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball Symbol U6 U7 U8 U9 GNDT TPFOP3 GNDR TPFIN4
Type1 - AO/AI - AO/AI - AO/AI - AO/AI - AO/AI - -
Reference for Full Description Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 30 (page 88) Table 34 (page 95) Table 34 (page 95)
U10 GNDT U11 TPFON5 U12 GNDT U13 TPFIP5 U14 GNDT U15 TPFON6 U16 GNDT U17 GNDT
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.4
3.4.1
BGA23 Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the two designations. Signal naming conventions are as follows:
* Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
* Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.
* Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.
3.4.2
Signal Descriptions - RMII, SMII, and SS-SMII Configurations
Table 24. Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - BGA23 (Sheet 1 of 3)
Ball/Pin Designation BGA23 PQFP Reference Clock. E6, E12 44 6 REFCLK0 REFCLK1 I 50 MHz RMII reference clock is always required. RMII inputs are sampled on the rising edge of REFCLK, RMII outputs are sourced on the falling edge. See "Clock/SYNC Requirements" on page 125. for detailed CLK requirements. Transmit Data - Port 0. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 0 are clocked in synchronously to REFCLK. Transmit Data - Port 1. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 1 are clocked in synchronously to REFCLK Transmit Data - Port 2. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 2 are clocked in synchronously to REFCLK. Symbol Type1 Signal Description2,3
E2, F4 C3, D4 B5 A4
61 62 52 53 42 43
TxData0_0 TxData0_1 TxData1_0 TxData1_1 TxData2_0 TxData2_1
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
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Table 24. Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - BGA23 (Sheet 2 of 3)
Ball/Pin Designation BGA23 D8, A6 A11, C10 B13, D11 D13, A16 E14, C16 E3, B2, C6, A7, B11, A14, C14, D16 C2, B1 A3, B4 B6, C7 D9, B9 A13, C12 B14, B15 PQFP 34 35 22 23 13 14 4 5 203 204 60 51 41 33 21 12 3 202 55 54 46 45 37 36 28 27 16 15 8 7 TxData3_0 TxData3_1 TxData4_0 TxData4_1 TxData5_0 TxData5_1 TxData6_0 TxData6_1 TxData7_0 TxData7_1 TxEN0 TxEN1 TxEN2 TxEN3 TxEN4 TxEN5 TxEN6 TxEN7 RxData0_0 RxData0_1 RxData1_0 RxData1_1 RxData2_0 RxData2_1 RxData3_0 RxData3_1 RxData4_0 RxData4_1 RxData5_0 RxData5_1 Transmit Data - Port 3. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to REFCLK. Transmit Data - Port 4. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to REFCLK. Transmit Data - Port 5. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to REFCLK. Transmit Data - Port 6. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to REFCLK. Transmit Data - Port 7. I, ID Inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to REFCLK. Symbol Type1 Signal Description2,3
Transmit Enable - Ports 0-7. I, ID Active High input enables respective port transmitter. This signal must be synchronous to the REFCLK.
O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID
Receive Data - Port 0. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 1. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 2. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 3. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 4. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 24. Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - BGA23 (Sheet 3 of 3)
Ball/Pin Designation BGA23 C15, B17 E16, F14 E4, C4, A5, B8, B12, D12, B16, E15 PQFP 206 205 198 197 58 49 39 31 17 10 1 200 RxData6_0 RxData6_1 RxData7_0 RxData7_1 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 O, TS O, TS, ID O, TS O, TS, ID Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Carrier Sense/Receive Data Valid - Ports 0-7. O, TS, SL, ID On detection of valid carrier, these signals are asserted asynchronously with respect to REFCLK. CRS_DVn is de-asserted on loss of carrier, synchronous to REFCLK. Receive Error - Ports 0-7. These signals are synchronous to the respective REFCLK. Active High indicates that received code group is invalid, or that PLL is not locked. O, TS, SL, ID, I, ST The RxER signals have the following additional function pins: RxER0 (MDIX) RxER1 (PAUSE) RxER2 (PREASEL) RxER4 (FIFOSEL0) RxER5 (FIFOSEL1) RxER6 {LINKHOLD) 1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset. Symbol Type1 Signal Description2,3
D2, D5, D7, C8, A12, A15, A17, D17
59 50 40 32 20 11 2 201
RxER0 RxER1 RxER2 RxER3 RxER4 RxER5 RxER6 RxER7
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 25. Intel(R) LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions - BGA23
Ball/Pin Designation BGA23 E2, C3, B5, D8, A11, B13, D13, E14 E6, E12 PQFP 61 52 42 34 22 13 4 203 TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 Symbol Type1 Signal Description2
Transmit Data - Ports 0-7. I, ID These serial input streams provide data to be transmitted to the network. The LXT9785/9785E clocks the data in synchronously to REFCLK.
Reference Clock. 44 6 REFCLK0 REFCLK1 I The LXT9785/9785E always requires a 125 MHz reference clock input. Refer to Functional Description for detailed clock requirements. REFCLK0 and REFCLK1 are always connected regardless of sectionalization mode.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode.
Table 26. Intel(R) LXT9785/LXT9785E SMII Specific Signal Descriptions - BGA23
Pin/Ball Designation BGA23 PQFP SMII Synchronization. A6, C16 35 204 SYNC0 SYNC1 I, ID The MAC must generate a SYNC pulse every 10 REFCLK cycles to synchronize the SMII. SYNC0 is used when 1x8 port sectionalization is selected. SYNC0 and SYNC1 are to be used when 2x4 port sectionalization is chosen. Symbol Type1 Signal Description2,3
C2, A3, B6, D9, A13, B14, C15, E16
55 46 37 28 16 8 206 198
RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7
Receive Data - Ports 0-7. O, TS These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to RXCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. 3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware reset.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 27. Intel(R) LXT9785/LXT9785E SS-SMII Specific Signal Descriptions - BGA23
Ball/Pin Designation BGA23 A6, C16 PQFP SS-SMII Transmit Synchronization. 35 204 TxSYNC0 TxSYNC1 I, ID The MAC must generate a TxSYNC pulse every 10 TxCLK cycles to mark the start of TxData segments. TxSYNC0 is used when 1x8 port sectionalization is selected. SS-SMII Receive Synchronization. E4, B12 58 17 RxSYNC0 RxSYNC1 O, TS, ID The LXT9785/9785E generates these pulses every 10 RxCLK cycles to mark the start of RxData segments for the MAC. RxSYNC1 is used when 1x8 port sectionalization is selected. RxSYNC0 may not be used. These outputs are only enabled when SS-SMII mode is enabled. SS-SMII Transmit Clock. C8, D17 32 201 TxCLK0 TxCLK1 I, ID The MAC sources this 125 MHz clock as the timing reference for TxData and TxSYNC. Only TxCLK0 is used when 1x8 port sectionalization is selected. See "Clock/ SYNC Requirements" on page 125. for detailed clock requirements. SS-SMII Receive Clock. E3, B11 60 21 RxCLK0 RxCLK1 O, TS, ID The LXT9785/9785E generates these clocks, based on REFCLK, to provide a timing reference for RxData and RxSYNC to the MAC. RxCLK1 is used when 1x8 port sectionalization is selected. RxCLK0 may not be used. See "Clock/SYNC Requirements" on page 125. for detailed clock requirements. These outputs are only enabled when SSSMII mode is enabled. Symbol Type1 Signal Description2,3
B1, B4, C7, B9, C12, B15, B17, F14
54 45 36 27 15 7 205 197
RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 RxData7
Receive Data - Ports 0-7. O, TS, ID These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to REFCLK.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down modes and during H/W reset.
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Table 28. Intel(R) LXT9785/LXT9785E MDIO Control Interface Signals - BGA23
Ball/Pin Designation BGA23 PQFP Management Data Input/Output. F3, A10 64 25 MDIO0 MDIO1 I/O, TS, SL, IP Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Only MDIO0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses ports 4-7. Refer to Figure 21 "Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram" on page 140. Management Data Interrupt. When Register bit 18.1 = 1, an active Low output on this Pin indicates status change. Only MDINT0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDINT0 is associated with ports 0-3 and MDINT1 is associated with ports 4-7. Refer to Figure 21 "Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram" on page 140. Management Data Clock. E1, B10 63 24 MDC0 MDC1 Clock for the MDIO serial data channel. Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDC0 clocks ports 0-3 register accesses and MDC1 clocks ports 4-7 register accesses. Refer to Figure 21 "Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram" on page 140. Management Disable. When MDDIS is tied High, the MDIO port is completely disabled and the Hardware Control Interface pins set their respective bits at power up and reset. L1 84 MDDIS I, ST, ID When MDDIS is pulled Low at power up or reset, via the internal pull-down resistor or by tieing it to ground, the Hardware Control Interface Pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. Symbol Type1 Signal Description2,3,4
F1, C9
67 26
MDINT0 MDINT1
OD, TS, SL, IP
I, ST, ID
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. MDIO[0:1] and MDINT[0:1] outputs are three-stated in H/W Power-Down mode and during H/W reset. 4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15).
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 29. Intel(R) LXT9785/LXT9785E Signal Detect - BGA23
Ball/Pin Designation BGA23 PQFP Signal Detect 2.5 Volt Interface. SD input threshold voltage select. P1 95 SD_2P5V I, ST, ID Tie to VCCPECL = Select 2.5 V LVPECL input levels Float or Tie to GNDPECL = Select 3.3 V LVPECL input levels P2, N4, P3, N5, P15, P16, P17, N17 96 97 100 101 161 162 165 166 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 Signal Detect - Ports 0-7. Signal Detect input from the fiber transceiver (these inputs are only active for ports operating in fiber mode). I Logic High = Normal operation (the process of searching for receive idles for the purpose of bringing link up is initiated) Logic Low = Link is declared lost Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. 3. Tie SD[0:7] inputs to GNDPECL if unused.
Table 30. Intel(R) LXT9785/LXT9785E Network Interface Signal Descriptions - BGA23
Ball/Pin Designation Symbol BGA23 T2, U1, T3, R4, T6, U5, U7, T7, T10, R10, T11, U11, T14,U15, R14, T15 R2, T1, U3, T4, R6, T5, T8, R8, T9, U9, U13, T12, R12, T13, R16, T16 PQFP 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 TPFOP0, TPFON0 TPFOP1, TPFON1 TPFOP2, TPFON2 TPFOP3, TPFON3 TPFOP4, TPFON4 TPFOP5, TPFON5 TPFOP6, TPFON6 TPFOP7, TPFON7 TPFIP0, TPFIN0 TPFIP1, TPFIN1 TPFIP2, TPFIN2 TPFIP3, TPFIN3 TPFIP4, TPFIN4 TPFIP5, TPFIN5 TPFIP6, TPFIN6 TPFIP7, TPFIN7 Twisted-Pair/Fiber Outputs2, Positive & Negative, Ports 0-7. AO/AI During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFO pins produce differential LVPECL outputs for fiber transceivers. Twisted-Pair/Fiber Inputs3, Positive & Negative, Ports 0-7. AI/AO During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential 100BASE-TX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFI pins receive differential LVPECL inputs from fiber transceivers. Type1 Signal Description
1. Type Column Coding: AI = Analog Input, AO = Analog Output. 2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode]. 3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is, twisted-pair, non-crossover MDI mode].
88
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 31. Intel(R) LXT9785/LXT9785E JTAG Test Signal Descriptions - BGA23
Ball/Pin Designation BGA23 N14 N15 N16 M16 M17 PQFP 167 168 169 170 171 TDI TDO TMS TCK TRST I, ST, IP O, TS I, ST, IP I, ST, ID I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for JTAG test. Test Reset. Reset input for JTAG test. Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT = Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. TDO output is three-stated in H/W Power-Down mode and during H/W reset.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23 (Sheet 1 of 4)
Ball/Pin Designation BGA23 PQFP Tx Output Slew Controls 0 and 1 Defaults. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 27.11:10 for all ports. These register bits can be read and overwritten after startup / reset. N3, M4 94 93 TxSLEW_0 TxSLEW_1 These pins select the TX output slew rate for all ports (rise and fall time) as follows: I, ST, ID TxSLEW_1 0 0 1 1 Pause Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 4.10 for all ports. This register bit can be read and overwritten after startup / reset. D5 50 PAUSE ID, I, ST When High, the LXT9785/9785E advertises Pause capabilities on all ports during auto-negotiation. This pin is shared with RMII-RxER1. An external pullup resistor (see applications section for value) can be used to set Pause active while RxER1 is three-stated during H/W reset. If no pull-up is used, the default Pause state is set inactive via the internal pull-down resistor. Power-Down. L14 174 PWRDWN I, ST, ID When High, forces the LXT9785/9785E into global power-down mode. Pin is not on JTAG chain. Reset. M15 175 RESET I, ST, IP This active low input is ORed with the control register Reset Register bit 0.15. When held Low, all outputs are forced to inactive state. Pin is not on JTAG chain. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 3.3 ns 3.6 ns 3.9 ns 4.2 ns Symbol Type1 Signal Description2
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23 (Sheet 2 of 4)
Ball/Pin Designation BGA23 PQFP Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. I, ST, ID Port 0 Address = Base Port 1 Address = Base + 1 Port 2 Address = Base + 2 Port 3 Address = Base + 3 Port 4 Address = Base + 4 Port 5 Address = Base + 5 Port 6 Address = Base + 6 Port 7 Address = Base + 7 Mode Select[1:0]. 00 = RMII L17, L16 178 177 MODESEL_1 MODESEL_0 01 = SMII I, ST, ID 10 = SS-SMII 11 = Reserved All ports are configured the same. Interfaces cannot be mixed and must be all RMII, SMII, or SS-SMII. Sectionalization Select. L15 176 SECTION I, ST, ID This pin selects sectionalization into separate ports. 0 = 1x8 ports, 1 = 2x4 ports Auto MDI/MDIX Enable Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 27.9 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 40 "Intel(R) LXT9785/LXT9785E MDIX Selection" on page 119. When active (High), automatic MDI crossover (MDIX) (regardless of segmentation) is selected for all ports. When inactive (Low) MDIX is selected according to the MDIX pin. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. Symbol Type1 Signal Description2
L4, M2, M3, N1, N2
88 89 90 91 92
ADD_4 ADD_3 ADD_2 ADD_1 ADD_0
K1
83
AMDIX_EN
I, ST, IP
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23 (Sheet 3 of 4)
Ball/Pin Designation BGA23 PQFP MDIX Select Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 27.8 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 40 "Intel(R) LXT9785/LXT9785E MDIX Selection" on page 119. When AMDIX_EN is active this pin is ignored. D2 59 MDIX I, ID, ST When AMDIX_EN is inactive, all ports are forced to the MDI or the MDIX function regardless of segmentation. If this pin is active (high), MDI crossover (MDIX) is selected. If this pin is inactive, non-crossover MDI mode is set. This pin is shared with RMII-RxER0. An external pullup resistor (see applications section for value) can be used to set MDIX active while RxER0 is three-stated during H/W reset. If no pull-up is used, the default MDIX state is set inactive via the internal pull-down resistor. Do not tie this pin directly to VCCIO (vs. using a pull-up) in non-RMII modes. Global Port Configuration Defaults 1-3. These pins are read at startup or reset. Their value at that time is used to set the default state of register bits shown in Table 42 "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129 for all ports. These register bits can be read and overwritten after startup / reset. When operating in Hardware Control Mode, these pins provide configuration control options for all the ports (refer to Table 42 "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129 for details). Global FX/TP Enable Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 16.0 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 92 "Port Configuration Register (Address 16, Hex 10)" on page 207. This input selects whether all the ports are defaulted to TP vs. FX mode. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. Symbol Type1 Signal Description2
L2, L3, M1
85 86 87
CFG_3 CFG_2 CFG_1
I, ST, ID
M14
173
G_FX/TP
I, ST, ID
92
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 32. Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - BGA23 (Sheet 4 of 4)
Ball/Pin Designation BGA23 PQFP FIFO Select <1:0>. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 18.15:14 for all ports. These register bits can be read and overwritten after startup/reset. A15 A12 11 20 FIFOSEL1 FIFOSEL0 I, ID, ST These pins are shared with RMII-RxER<5:4>. An external pull-up resistor (see applications section for value) can be used to set FIFO Select<1:0> to active while RxER<5:4> are three-stated during hardware reset. If no pull-up is used, the default FIFO select state is set via the internal pull-down resistors. See Table 36 "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Configurations" on page 97. Preamble Select. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 16.5 for all ports. This register bit can be read and overwritten after startup/reset. D7 40 PREASEL I, ID, ST This pin is shared with RMII-RxER2. An external pullup resistor (see applications section for value) can be used to set Preamble Select to active while RxER2 is three-stated during hardware reset. If no pull-up is used, the default Preamble Select state is set via the internal pull-down resistors. Note: Preamble select has no effect in 100 Mbps operation. LINKHOLD Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 0.11 for all ports. This register bit can be read and overwritten after startup / reset. When High, the LXT9785/9785E powers down all ports. This pin is shared with RMII-RxER6. An external pullup resistor (see applications section for value) can be used to set LINKHOLD active while RxER6 is tri-stated during H/W reset. If no pull-up is used, the default LINKHOLD state is set inactive via the internal pulldown resistor. Symbol Type1 Signal Description2
A17
2
LINKHOLD
I, ID, ST
1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 33. Intel(R) LXT9785/LXT9785E LED Signal Descriptions - BGA23 (Sheet 1 of 2)
Ball/Pin Designation BGA23 PQFP Port 0 LED Drivers 1-3. K3, K2, J1 82 81 80 LED0_1 LED0_2 LED0_3 OD, TS, SL, IP These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 1 LED Drivers 1-3. J4, J3, H1 77 76 75 LED1_1 LED1_2 LED1_3 OD, TS, SL, IP These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 2 LED Drivers 1-3. H2, H3, G1 73 72 71 LED2_1 LED2_2 LED2_3 OD, TS, SL, IP These pins drive LED indicators for Port 2. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 3 LED Drivers 1-3. F2, G3, G4 70 69 68 LED3_1 LED3_2 LED3_3 OD, TS, SL, IP These pins drive LED indicators for Port 3. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 4 LED Drivers 1-3. K16, K17, J17 180 181 182 LED4_1 LED4_2 LED4_3 OD, TS, SL, IP These pins drive LED indicators for Port 4. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. 4.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 33. Intel(R) LXT9785/LXT9785E LED Signal Descriptions - BGA23 (Sheet 2 of 2)
Ball/Pin Designation BGA23 PQFP Port 5 LED Drivers 1-3. J15, J16, H17 185 186 187 LED5_1 LED5_2 LED5_3 OD, TS, SL, IP These pins drive LED indicators for Port 5. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 6 LED Drivers 1-3. H15, H16, G17 189 190 191 LED6_1 LED6_2 LED6_3 OD, TS, SL, IP These pins drive LED indicators for Port 6. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 7 LED Drivers 1-3. G15, F17, F16 192 193 194 LED7_1 LED7_2 LED7_3 OD, TS, SL, IP These pins drive LED indicators for Port 7. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96 "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Symbol Type1 Signal Description2,3
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. The LED outputs are three-stated in H/W Power-Down mode and during H/W reset. 4.
Table 34. Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - BGA23 (Sheet 1 of 2)
Ball/Pin Designation Symbol BGA23 G13, J14, F5, J5 PQFP 65, 78, 184, 196 VCCD Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. A2, A8, C1, C11, D14 18, 29, 47, 56, 208 VCCIO +2.5/3.3 V supply for digital I/O circuits. The digital input circuits running off of this rail, having a TTL-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 V, when the IO supply is 3.3 V, and 2.5/3.3/5.0 V when 2.5 V. Digital Power Supply - PECL Signal Detect Inputs. L13, L5 98, 164 VCCPECL +2.5/3.3 V supply for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these pins to GNDPECL to save power. Analog Power Supply - Receive. +2.5 V supply for all analog receive circuits. Type Signal Description
N13, P4, P7, P8, P9, P10, P11, P12
103, 116, 117, 130, 131, 144, 145, 158
VCCR
-
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 34. Intel(R) LXT9785/LXT9785E Power Supply Signal Descriptions - BGA23 (Sheet 2 of 2)
Ball/Pin Designation Symbol BGA23 N6, N7, N9, N11, N12 A1, A9, B3, B7, C5, C13, C17, D1, D3, D6, D10, D15, E5, E7, E9, E11, E13, E17, F13, H8, H9, H10, J8, J9, J10, K8, K9, K10 PQFP 109, 123, 138, 152 VCCT Analog Power Supply - Transmit. +2.5 V supply for all analog transmit circuits. Type Signal Description
Digital Ground. 66, 79, 183, 195 GNDD Ground return for core digital supplies (VCCD). All ground pins can be tied together using a single ground plane.
9, 19, 30, 38, 48, 57, 74, 188, 199, 207 M5, M13 P5, P6, P13, R7, R9, R11, R13, U8 P14, R1, R3, R5, R15, R17, T17, U2, U4, U6, U10, U12, U14, U16, U17 K14 99, 163 106, 112, 120, 126, 135, 141, 149, 155
GNDIO
-
Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO). Digital GND - PECL Signal Detect Inputs. Ground return for PECL Signal Detect input circuits. Analog Ground - Receive.
GNDPECL
-
GNDR
-
Ground return for receive analog supply. All ground pins can be tied together using a single ground plane.
113, 127, 134, 148
Analog Ground - Transmit. GNDT Ground return for transmit analog supply. All ground pins can be tied together using a single ground plane.
Substrate Ground. 179 SGND Ground for chip substrate. All ground pins can be tied together using a single ground plane.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 35. Intel(R) LXT9785/LXT9785E Unused/Reserved Pins - BGA23
Pin/Ball Designation Symbol BGA23 F15, G2, G5, G14, G16, H4, H14, J2, J13, K4, K15 PQFP Type1 Signal Description
N/C
N/C
-
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown 2.
Table 36. Intel(R) LXT9785/LXT9785E Receive FIFO Depth Configurations
FIFOSEL1 0 0 1 1 FIFOSEL0 0 1 0 1 Register 18.15 Value 1 1 0 0 Register 18.14 Value 0 1 0 1
Datasheet
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.5
BGA15 Ball Assignments
The following figure and tables provide the BGA15 ball locations and signal names arranged in alphanumeric order as follows:
* Figure 6 "Intel(R) LXT9785MBC 196-Ball BGA15 Assignments (Top View)" * Table 37, "Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name"
on page 99
* Table 38, "Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location
(SMII/SS-SMII)" on page 103 Figure 6. Intel(R) LXT9785MBC 196-Ball BGA15 Assignments (Top View)
1 A B C D E F G H J K L M N P
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1
2
A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2
3
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3
4
A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4
5
A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5
6
A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 L6 M6 N6 P6
7
A7 B7 C7 D7 E7 F7 G7 H7 J7 K7 L7 M7 N7 P7
8
A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 L8 M8 N8 P8
9
A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 L9 M9 N9 P9
10
A10 B10
11
12
13
14 A B C D E F G H J K L M N P
A11 A12 A13 A14 B11 B12 B13 B14
C10 C11 C12 C13 C14 D10 D11 D12 D13 D14 E10 F10 E11 E12 E13 E14 F11 F12 F13 F14
G10 G11 G12 G13 G14 H10 H11 H12 H13 H14 J10 J11 J12 J13 J14
K10 K11 K12 K13 K14 L10 L11 L12 L13 L14
M10 M11 M12 M13 M14 N10 N11 N12 N13 N14 P10 P11 P12 P13 P14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
B1532-01
98
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
3.5.1
BGA15 Ball List
The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: Table 37 "Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name" Table 38 "Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII)"
Table 37. Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name
Signal Name ADD_3 ADD_4 AMDIX_EN AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS CFG_1 Ball P10 N10 K8 D12 E12 F12 G12 H12 J12 K12 L12 E11 F9 F10 F11 G9 G10 G11 H9 H10 H11 J9 J10 J11 K11 L11 M10 Type I, ST, ID I, ST, ID I, ST, IP - - - - - - - - - - - - - - - - - - - - - - - I, ST, ID Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Signal Name CFG_2 CFG_3 FIFOSEL0 FIFOSEL1 GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD Ball L9 M9 F1 C1 A1 A2 A3 B1 B2 B5 B10 D9 D11 E5 E6 E9 E10 F5 F6 F7 F8 G4 G6 G7 G8 H6 H7 H8 J5 Type I, ST, ID I, ST, ID I, ID I, ID - - - - - - - - - - - - - - - - - - - - - - - - - Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Datasheet
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal Name GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD LED0_1
Ball J6 J7 J8 K5 K6 K9 K10 L2 N1 N11 P1 P11 N9
Type - - - - - - - - - - - - OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Signal Name LED6_1
Ball
Type OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP ID I, ST, ID OD, TS, SL, IP IO, TS, SL, IP I, ST, ID I, ST, ID - - - - - - - - - - - - - - - - - - - -
Reference for Full Description Table 39 on page 109
A7
LED6_2
B7
Table 39 on page 109
LED7_1
B6
Table 39 on page 109
LED7_2 LINKHOLD MDC MDINT
A6 B3 P4 P5 N5 C9 E8 C4 C7 D1 D2 D5 D6 D8 D10 E4 E7 G2 G5 H1 H5 J4 K4 K7 L1 L6 L8
Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Table 39 on page 109 MDIO Table 39 on page 109 ModeSel_0 Table 39 on page 109 ModeSel_1 N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C Table 39 on page 109 N/C N/C
LED0_2
P9
LED1_1
N8
LED1_2
P8
LED2_1
P7
LED2_2
N7
LED3_1
P6
LED3_2
N6
LED4_1
B9
LED4_2
A9
LED5_1
B8
LED5_2
A8
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal Name N/C N/C N/C N/C N/C N/C N/C N/C REFCLK0 REFCLK1 RESET RXCLK RxData0_S RxData0_SS RxData1_S RxData1_SS RxData2_S RxData2_SS RxData3_S RxData3_SS RxData4_S RxData4_SS RxData5_S RxData5_SS RxData6_S RxData6_SS RxData7_S RxData7_SS RxSYNC SGND SYNC/ TXSYNC
Ball L10 M4 M5 M6 M7 M8 P2 P3 L4 C3 C10 G1 N3 M3 M2 M1 K2 J2 H3 H2 F2 F3 E3 C2 B4 A4 C5 C6 E1 C8 K1
Type - - - - - - - - I I I, ST, IP O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS, ID O, TS O, TS O, TS O, TS, ID O, TS O, TS, ID O, TS, ID - I, ID
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Signal Name TCK TDI TDO TMS TPIN0 TPIN1 TPIN2 TPIN3 TPIN4 TPIN5 TPIN6 TPIN7 TPIP0 TPIP1 TPIP2 TPIP3 TPIP4 TPIP5 TPIP6 TPIP7 TPON0 TPON1 TPON2 TPON3 TPON4 TPON5 TPON6 TPON7 TPOP0 TPOP1 TPOP2 TPOP3 TPOP4 TPOP5 TPOP6 TPOP7
Ball A11 C12 C11 B11 N12 M13 L14 H13 G13 D14 C13 B12 P12 M14 L13 H14 G14 D13 C14 A12 N13 P14 K14 J13 F13 E14 A14 B13 P13 N14 K13 J14 F14 E13 B14 A13
Type I, ST, ID I, ST, IP O, TS I, ST, IP AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AI/AO AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI AO/AI
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
AO, AI Table 39 on page 109 AO/AI AO/AI AO/AI Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Signal Name TRST TXCLK TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 TXSLEW_0 TXSLEW_1 VCCD VCCD VCCIO VCCIO VCCIO VCCIO VCCIO
Ball A10 J3 N4 N2 K3 J1 G3 E2 D3 A5 M11 M12 D7 L7 D4 F4 H4 L3 L5
Type I, ST, IP I, ID I, ID I, ID I, ID I, ID I, ID I, ID I, ID I, ID I, ST, ID I,ST, ID - - - - - - -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
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Table 38 shows the ball locations and signal names arranged in order by ball location. Table 38. Intel(R) LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII)
Ball A1 A2 A3 A4 A5 A6 Signal Name GNDD GNDD GNDD RxData6_SS TxData7 LED7_2 Type - - - O, TS, ID I, ID OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, IP I, ST, ID AI/AO AO/AI AO/AI - - ID O, TS - OD, TS, SL, IP Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 B8 LED5_1 Ball Signal Name Type OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP - I, ST, IP AI/AO AO/AI AO/AI I, ID O, TS, ID I - O, TS O, TS, ID - - I, ST, ID I, ST, IP O, TS I, ST, IP AI/AO Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
B7
LED6_2
B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13
LED4_1 GNDD TMS TPIN7 TPON7 TPOP6 FIFOSEL1 RxData5_SS REFCLK1 N/C RxData7_S RxData7_SS N/C SGND ModeSel_0 RESET TDO TDI TPIN6
A7
LED6_1
A8
LED5_2
A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6
LED4_2 TRST TCK TPIP7 TPOP7 TPON6 GNDD GNDD LINKHOLD RxData6_S GNDD LED7_1
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9
Signal Name TPIP6 N/C N/C TxData6 VCCIO N/C N/C VCCD N/C GNDD N/C GNDD AVCC TPIP5 TPIN5 RxSYNC TxData5 RxData5_S N/C GNDD GNDD N/C ModeSel_1 GNDD
Type AI/AO - - I, ID - - - - - - - - - AI/AO AI/AO O, TS, ID I, ID O, TS - - - - I, ST, ID -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Ball E10 E11 E12 E13 E14 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5
Signal Name GNDD AVSS AVCC TPOP5 TPON5 FIFOSEL0 RxData4_S RxData4_SS VCCIO GNDD GNDD GNDD GNDD AVSS AVSS AVSS AVCC TPON4 TPOP4 RXCLK N/C TxData4 GNDD N/C
Type - - - AO/AI AO/AI I, ID O, TS O, TS, ID - - - - - - - - - AO/AI AO, AI O, TS, ID - I, ID - -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 J1
Signal Name GNDD GNDD GNDD AVSS AVSS AVSS AVCC TPIN4 TPIP4 N/C RxData3_SS RxData3_S VCCIO N/C GNDD GNDD GNDD AVSS AVSS AVSS AVCC TPIN3 TPIP3 TxData3
Type - - - - - - - AI/AO AI/AO - O, TS, ID O, TS - - - - - - - - - AI/AO AI/AO I, ID
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Ball J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11
Signal Name RxData2_SS TXCLK N/C GNDD GNDD GNDD GNDD AVSS AVSS AVSS AVCC TPON3 TPOP3 SYNC/ TXSYNC RxData2_S TxData2 N/C GNDD GNDD N/C AMDIX_EN GNDD GNDD AVSS
Type O, TS, ID I, ID - - - - - - - - - AO/AI AO/AI I, ID O, TS I, ID - - - - I, ST, IP - - -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7
Signal Name AVCC TPOP2 TPON2 N/C GNDD VCCIO REFCLK0 VCCIO N/C VCCD N/C CFG_2 N/C AVSS AVCC TPIP2 TPIN2 RxData1_SS RxData1_S RxData0_SS N/C N/C N/C N/C
Type - AO/AI AO/AI - - - I - - - - I, ST, ID - - - AI/AO AI/AO O, TS, ID O, TS O, TS, ID - - - -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
Ball M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5
Signal Name N/C CFG_3 CFG_1 TXSLEW_0 TXSLEW_1 TPIN1 TPIP1 GNDD TxData1 RxData0_S TxData0 MDIO
Type - I, ST, ID I, ST, ID I, ST, ID I,ST, ID AI/AO AI/AO - I, ID O, TS I, ID IO, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, ID - AI/AO AO/AI AO/AI -
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
N6
LED3_2
N7
LED2_2
N8
LED1_1
N9 N10 N11 N12 N13 N14 P1
LED0_1 ADD_4 GNDD TPIN0 TPON0 TPOP1 GNDD
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Intel(R) LXT9785 and Intel(R) LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Ball P2 P3 P4 P5
Signal Name N/C N/C MDC MDINT
Type - - I, ST, ID OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP OD, TS, SL, IP I, ST, ID - AI/AO AO/AI AO/AI
Reference for Full Description Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109 Table 39 on page 109
P6
LED3_1
P7
LED2_1
P8
LED1_2
P9 P10 P11 P12 P13 P14
LED0_2 ADD_3 GNDD TPIP0 TPOP0 TPON1
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3.6
3.6.1
BGA15 Signal Descriptions
Signal Name Conventions
Signal names may contain either a port designation or a serial designation, or a combination of the two designations. Signal naming conventions are as follows:
* Port Number Only. Individual signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit Enable signals would be identified as TxEN0, TxEN1, and TxEN2.
* Serial Number Only. A set of signals which are not tied to any specific port are designated by
the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3. signal is designated in the following order: Signal Mnemonic, Port Designation, an underscore, and the serial designation. For example, a set of three Port Configuration signals would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and RxData2_0 and RxData2_1.
* Port and Serial Number. In cases where each port is assigned a set of multiple signals, each
3.6.2
Signal Descriptions - SMII and SS-SMII Configurations
Table 39 provides the BGA15 signal descriptions.
Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 1 of 7)
BGA15 Ball Designation Symbol Type Signal Description
SMII/SS-SMII Common Signal Descriptions N4, N2, K3, J1, G3, E2, D3, A5 TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 REFCLK1 REFCLK0
Transmit Data - Ports 0-7. I, ID These serial input streams provide data to be transmitted to the network. The LXT9785/9785E clocks the data in synchronously to REFCLK.
Reference Clock. C3 L4 I The LXT9785/9785E always requires a 125 MHz reference clock input. Refer to Section 4.4.2, "Clock/SYNC Requirements" on page 125 for detailed clock requirements.
SMII Specific Signal Descriptions SMII Synchronization. K1 SYNC I, ID The MAC must generate a SYNC pulse every 10 REFCLK cycles to synchronize the SMII.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 2 of 7)
BGA15 Ball Designation N3, M2, K2, H3, F2, E3, B4, C5 Symbol RxData0_S RxData1_S RxData2_S RxData3_S RxData4_S RxData5_S RxData6_S RxData7_S Type Signal Description
Receive Data - Ports 0-7. O, TS These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to REFCLK.
SS-SMII Specific Signal Descriptions SS-SMII Transmit Synchronization. K1 TxSYNC I, ID The MAC must generate a TxSYNC pulse every 10 TxCLK cycles to mark the start of TxData segments. SS-SMII Receive Synchronization. E1 RxSYNC O, TS, ID The LXT9785/9785E generates these pulses every 10 RxCLK cycles to mark the start of RxData segments for the MAC. SS-SMII Transmit Clock. J3 TxCLK I, ID The MAC sources this 125 MHz clock as the timing reference for TxData and TxSYNC. See "Clock/SYNC Requirements" on page 125 for detailed clock requirements. SS-SMII Receive Clock. G1 RxCLK O, TS, ID The LXT9785/9785E generates these clocks, based on REFCLK, to provide a timing reference for RxData and RxSYNC to the MAC. See "Clock/SYNC Requirements" on page 125 for detailed clock requirements. These outputs are only enabled when SS-SMII mode is enabled.
M3, M1, J2, H2, F3, C2, A4, C6
RxData0_SS RxData1_SS RxData2_SS RxData3_SS RxData4_SS RxData5_SS RxData6_SS RxData7_SS
Receive Data - Ports 0-7. O, TS, ID These serial output streams provide data received from the network. The LXT9785/9785E drives the data out synchronously to REFCLK.
MDIO Control Interface Signal Descriptions Management Data Input/Output. N5 MDIO I/O, TS, SL, IP Bidirectional serial data channel for communication between the PHY and MAC or switch ASIC. Refer to Figure 21 on page 140. Management Data Interrupt. When Register bit 18.1 = 1, an active Low output on this Pin indicates status change. Refer to Figure 21 on page 140.
P5
MDINT
OD, TS, SL, IP
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 3 of 7)
BGA15 Ball Designation Symbol Type Signal Description Management Data Clock. P4 MDC I, ST, ID Clock for the MDIO serial data channel. Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port sectionalization is selected. In 2x4 port sectionalization mode, MDC0 clocks ports 0-3 register accesses and MDC1 clocks ports 4-7 register accesses. Refer to Figure 21 on page 140.
Network Interface Signal Description P13, N13, N14, P14, K13, K14, J14, J13, F14, F13, E13, E14, B14, A14, A13, B13 P12, N12, M14, M13, L13, L14, H14, H13, G14, G13, D13, D14, C14, C13, A12, B12 TPOP0, TPON0 TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 TPOP4, TPON4 TPOP5, TPON5 TPOP6, TPON6 TPOP7, TPON7 TPIP0, TPIN0 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 TPIP4, TPIN4 TPIP5, TPIN5 TPIP6, TPIN6 TPIP7, TPIN7
Twisted-Pair Outputs2, Positive & Negative, Ports 0-7. AO/AI During 100BASE-TX or 10BASE-T operation, TPO pins drive 802.3 compliant pulses onto the line.
Twisted-Pair Inputs3, Positive & Negative, Ports 0-7. AI/AO During 100BASE-TX or 10BASE-T operation, TPI pins receive differential 100BASE-TX or 10BASE-T signals from the line.
JTAG Test Signal Description C12 C11 B11 A11 A10 TDI TDO TMS TCK TRST I, ST, IP O, TS I, ST, IP I, ST, ID I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for JTAG test. Test Reset. Reset input for JTAG test.
Miscellaneous Signal Description 1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 4 of 7)
BGA15 Ball Designation Symbol Type Signal Description Tx Output Slew Controls 0 and 1 Defaults. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 27.11:10 for all ports. These register bits can be read and overwritten after startup / reset. M11, M12 TxSLEW_0 TxSLEW_1 These pins select the TX output slew rate for all ports (rise and fall time) as follows: I, ST, ID TxSLEW_1 0 0 1 1 Reset. C10 RESET I, ST, IP This active low input is ORed with the control register Reset Register bit 0.15. When held Low, all outputs are forced to inactive state. Pin is not on JTAG chain. Address <4:3>. Sets base address to one of the following four possible addresses: * 00000 * 01000 * 10000 * 11000 N10, P10 ADD_4 ADD_3 I, ST, ID Each port adds its port number (starting with 0) to this address to determine its PHY address. Port 0 Address = Base Port 1 Address = Base + 1 Port 2 Address = Base + 2 Port 3 Address = Base + 3 Port 4 Address = Base + 4 Port 5 Address = Base + 5 Port 6 Address = Base + 6 Port 7 Address = Base + 7 Mode Select[1:0]. 00 = Reserved E8 C9, MODESEL_1 MODESEL_0 01 = SMII I, ST, ID 10 = SS-SMII 11 = Reserved All ports are configured the same. Interfaces cannot be mixed and must be all SMII or SS-SMII. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown. TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 3.3 ns 3.6 ns 3.9 ns 4.2 ns
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 5 of 7)
BGA15 Ball Designation Symbol Type Signal Description Auto MDI/MDIX Enable Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 27.9 for all ports. These register bits can be read and overwritten after startup / reset. Refer to Table 40 on page 119. When active (High), automatic MDI crossover (MDIX) (regardless of segmentation) is selected for all ports. When inactive (Low) MDIX is selected according to the MDIX pin. Global Port Configuration Defaults 1-3. These pins are read at startup or reset. Their value at that time is used to set the default state of register bits shown in Table 42, "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129 for all ports. These register bits can be read and overwritten after startup / reset. When operating in Hardware Control Mode, these pins provide configuration control options for all the ports (refer to page 129 for details). FIFO Select <1:0>. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 18.15:14 for all ports. These register bits can be read and overwritten after startup/reset. C1, F1 FIFOSEL1 FIFOSEL0 I, ID, ST These pins are shared with RMII-RxER<5:4>. An external pull-up resistor (see applications section for value) can be used to set FIFO Select<1:0> to active while RxER<5:4> are three-stated during hardware reset. If no pull-up is used, the default FIFO select state is set via the internal pull-down resistors. See Table 36, "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Configurations" on page 97. LINKHOLD Default. This pin is read at startup or reset. Its value at that time is used to set the default state of Register bit 0.11 for all ports. This register bit can be read and overwritten after startup / reset. When High, the LXT9785/ 9785E powers down all ports. This pin is shared with RMII-RxER6. An external pull-up resistor (see applications section for value) can be used to set LINKHOLD active while RxER6 is three-stated during H/W reset. If no pull-up is used, the default LINKHOLD state is set inactive via the internal pull-down resistor.
K8
AMDIX_EN
I, ST, IP
M10, L9, M9
CFG_1 CFG_2 CFG_3
I, ST, ID
B3
LINKHOLD
I, ID, ST
LED Signal Descriptions Port 0 LED Drivers 1-2. N9, P9 LED0_1 LED0_2 OD, TS, SL, IP These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details).
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 6 of 7)
BGA15 Ball Designation Symbol Type Signal Description Port 1 LED Drivers 1-2. N8, P8 LED1_1 LED1_2 OD, TS, SL, IP These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 2 LED Drivers 1-2. P7, N7, LED2_1 LED2_2 OD, TS, SL, IP These pins drive LED indicators for Port 2. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 3 LED Drivers 1-2. P6, N6 LED3_1 LED3_2 OD, TS, SL, IP These pins drive LED indicators for Port 3. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 4 LED Drivers 1-2. B9, A9 LED4_1 LED4_2 OD, TS, SL, IP These pins drive LED indicators for Port 4. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 5 LED Drivers 1-2. B8, A8 LED5_1 LED5_2 OD, TS, SL, IP These pins drive LED indicators for Port 5. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 6 LED Drivers 1-2. A7, B7 LED6_1 LED6_2 OD, TS, SL, IP These pins drive LED indicators for Port 6. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details). Port 7 LED Drivers 1-2. B6, A6 LED7_1 LED7_2 OD, TS, SL, IP These pins drive LED indicators for Port 7. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213 for details).
Power Supply Signal Descriptions D12, E12, F12, G12, H12, J12, K12, L12, Analog Power Supply. +2.5 V supply for analog circuits.
AVCC
-
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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Table 39. Intel(R) LXT9785 BGA15 Signal Descriptions (Sheet 7 of 7)
BGA15 Ball Designation E11, F9, F10, F11, G9, G10, G11, H9, H10, H11, J9, J10, J11, K11, L11 D7, L7 Symbol Type Signal Description
Analog Ground. AVSS - Ground return for analog supply (AVCC). all grounds can be tied together using a single ground plane. Digital Power Supply - Core. +2.5 V supply for core digital circuits. Digital Power Supply - I/O Ring. +2.5/3.3 V supply for digital I/O circuits. The digital input circuits running off of this rail, having a TTL-level threshold and over-voltage protection, may be interfaced with 3.3/5.0 V, when the IO supply is 3.3 V, and 2.5/3.3/5.0 V when 2.5 V.
VCCD
-
D4, F4, H4, L3, L5,
VCCIO
-
A1, A2, A3, B1, B2, B5, B10, D9, D11, E5, E6, E9, E10, F5, F6, F7, F8, G4, G6, G7, G8, H6, H7, H8, J5, J6, J7, J8, K5, K6, K9, K10, L2, N1, N11, P1, P11 C8
Digital Ground. GNDD - Ground return for core digital supplies (VCCD). All ground pins can be tied together using a single ground plane.
Substrate Ground. SGND - Ground for chip substrate. All ground pins can be tied together using a single ground plane.
Unused/Reserved Balls C4, C7, D1, D2, D5, D6, D8, D10, E4, E7, G2, G5, H1, H5, J4, K4, K7, L1, L6, L8, L10, M4, M5, M6, M7, M8, P2, P3
N/C
-
No Connection.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pullDown.
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4.0
4.1
Functional Description
Introduction
The Intel(R) LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10 Mbps and 100 Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The device incorporates a Serial Media Independent Interface (SMII), Source Synchronous-Serial Media Independent Interface (SS-SMII), and a Reduced Serial Independent Interface (RMII) to enable each individual network port to interface with multiple 10/100 MACs. Each port directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785/9785E also supports 100BASE-FX operation via an LVPECL interface. The device has a 241-ball BGA, a 208-pin QFP, or a 196-ball BGA package. The 196-ball BGA package (BGA15) is a reduced feature-set product. The BGA15 package does not support the following features:
* * * * *
RMII Fiber Sectionalization Third LED port (only two LEDs per port) Hardware control pins: -- PAUSE -- MDIX -- MDDIS -- PWRDWN -- Lower three PHY address (out of five PHY address bits)
* Extended temperature
Note: Unless otherwise noted, all information in this document applies to the LXT9785 and LXT9785E.
4.1.1
OSPTM Architecture
The Intel LXT9785/LXT9785E incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result is improved receiver noise and cross-talk performance. The OSP architecture also requires substantially less computational logic than traditional DSPbased designs. The result is lower power consumption and reduced logic switching noise generated by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable source of EMI when generated from the device's power supplies.
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The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance and power consumption.
4.1.2
Comprehensive Functionality
The LXT9785/LXT9785E performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT9785/LXT9785E reads its configuration inputs to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT9785/LXT9785E auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT9785/LXT9785E automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. The LXT9785/LXT9785E provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
4.1.2.1
Sectionalization
The LXT9785/LXT9785E's sectional design allows flexibility with large multiport MACs and ASICs. With the use of the Section pin, the LXT9785/LXT9785E can be configured into a single 8port or two separate 4-port sections, each with its own MDIO (with separate MDC clock) and MII data (with separate REFCLK/TxCLK/RxCLK clocks) interfaces. See Figure 16, "Intel(R) LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram" on page 134, Figure 21, "Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram" on page 140, and Figure 26, "Intel(R) LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram" on page 144.
Note:
The BGA15 package does not support sectionalization.
4.2
4.2.1
Interface Descriptions
10/100 Network Interface
The LXT9785/LXT9785E supports 10 Mbps and 100 Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair, or 100 Mbps (100BASE-FX) Ethernet over fiber media. Each network interface port consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. The LXT9785/LXT9785E pinout is designed to interface seamlessly with dual-high stacked RJ-45 connectors. Refer to Table 11, "Intel(R) LXT9785/ LXT9785E Network Interface Signal Descriptions - PQFP" on page 42 for specific pin assignments. The LXT9785/LXT9785E output drivers generate either 100BASE-TX, 10BASE-T, or 100BASEFX output. When not transmitting data, the device generates IEEE 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.
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Figure 7. Intel(R) LXT9785/LXT9785E Interfaces
TXENn TXDn_0 TXDn_1 TPFOPn TPFONn
Data Interface
TXCLK RXCLK RXDn_1 RXDn_0 RXERn CRS_DVn
Network Interface
TPFIPn TPFINn
MDIO Management Interface
MDIOn MDCn MDINTn MDDIS
Direct Drive
Port LEDs/ Controls
LEDn_2 LEDn_2 LEDn_3
Addr & MDIX/ Contr
MDIX_Enb Mode Select ADD<4:0>
VCCIO VCCD GNDD
+3.3 V OR +2.5 V +2.5 V
.01 uF
4.2.1.1
Twisted-Pair Interface
The LXT9785/LXT9785E supports either 100BASE-TX or 10BASE-T connections over 100 , Category 5, Unshielded Twisted-Pair (UTP). Only a transformer, RJ-45, and bypass capacitors are required to complete this interface. Using Intel's patented waveshaping technology, the transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 13, "Intel(R) LXT9785/LXT9785E Miscellaneous Signal Descriptions - PQFP" on page 43) allow the designer to match the output waveform to the magnetic characteristics. Both transmit and receive terminations are built into the LXT9785/LXT9785E so no external components are required between the LXT9785/LXT9785E and the external transformer. The transmitter uses a transformer with a center tap to help reduce power consumption. When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not transmitting data, the LXT9785/LXT9785E generates "IDLE" symbols.
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During 10 Mbps operation, LXT9785/LXT9785E encoded data is exchanged. When no data are being exchanged, the line is left in an idle state with NLPs transmitted to maintain link.
4.2.1.2
MDI Crossover (MDIX)
The LXT9785/LXT9785E crossover function, which is compliant to the IEEE 802.3, clause 23 standard, connects the transmit output of the device to the far-end receiver in a link segment. This function can be disabled via Register bits 27.9:8 or by using the hardware configuration pins.
Table 40. Intel(R) LXT9785/LXT9785E MDIX Selection
AMDIX_EN 0 0 1 MDIX 0 1 X MDIX Mode MDI forced MDIX forced Auto MDI/MDIX
Note:
The BGA15 package does not support MDIX hardware configuration. Software must be used to control the function after power-up.
4.2.1.3
Fiber Interface
The LXT9785/LXT9785E fiber ports are designed to interface with common industry-standard 3.3 V and 5 V fiber-optic transceivers. Each of the 8 ports incorporates a Low-Voltage PECL interface that complies with the ANSI X3.166 standard for seamless integration.
Note:
The BGA15 package does not support the fiber interface. Fiber mode is selected through Register bit 16.0 by the following two methods: 1. Configure Register bit 16.0 = 1 on a global basis (all 8 ports) by driving the Hardware Control pin G_FX/TP to a logic High value on power-up and/or reset. 2. Configure Register bit 16.0 = 1 on a per-port basis through the MDIO interface. The fiber interface is capable of full-duplex or half-duplex operation. In half duplex, operation collisions must be managed by external Layer 2 logic (MAC). Auto negotiation is not supported for fiber mode.
4.3
Media Independent Interface (MII) Interfaces
The LXT9785/LXT9785E supports Reduced MII or Serial MII, but not concurrently. The interface mode selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports. Refer to Table 41 for the mode select settings. Note: The BGA15 package does not support the RMII interface.
4.3.1
Global MII Mode Select
The mode select pins are used for MII interface configuration settings upon power-up sequencing. All ports are configured the same and cannot be intermixed.
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Table 41. Intel(R) LXT9785/LXT9785E MII Mode Select
ModeSel1 RMII1 SMII SS-SMII Reserved 0 0 1 1 ModeSel0 0 1 0 1
1. Invalid for the BGA15 package.
4.3.2
Internal Loopback
Register bit 0.14 must be set to enable internal loopback operation. Register bits 16.14 and 0.8 must be set for 10 Mbps operation. Intel recommends that auto-negotiation be disabled while internal loopback is enabled. The normal auto-negotiation process code word exchange cannot be completed.The following two-step sequence is recommended for the most efficient mode change when enabling forced 100 Mbps internal loopback mode directly from auto-negotiation mode: 1. Write Register 0 with 0x2100h (forced 100 Mbps), and 2. Write Register 0 with 0x6100h (enable internal loopback with forced 100 Mbps) This two-step process ensures the 100 Mbps link comes up quickly. If the one-write process of writing 0x6100h is followed, it may take up to 1.5 seconds before link is established and data is received on the port. The 1.5 second delay is due to the IEEE auto-negotiation Break Link Timer (BLT) requirement. The timer must expire before link is established when changing modes directly from auto-negotiation to internal loopback forced 100 Mbps mode. Use the above two-step process to eliminate the auto-negotiation BLT timer requirement.
Figure 8. Intel(R) LXT9785/LXT9785E Internal Loopback
LXT9785/9785E
RMII/ SMII/ SSSMII inter face
Fx Driver Digital Block Loopback Analog Block Tx Driver
4.3.3
RMII Data Interface
The LXT9785/LXT9785E provides a separate RMII for each network port, each complying with the RMII Specification, Revision 1.2. The RMII includes both a data interface and an MDIO management interface. The RMII Data Interface exchanges data between the LXT9785/LXT9785E and up to eight Media Access Controllers (MACs).
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4.3.4
4.3.4.1
Serial Media Independent Interface (SMII) and Source SynchronousSerial Media Independent Interface (SS-SMII)
SMII Interface
The LXT9785/LXT9785E provides an independent serial interface for each network port, complying with the Serial-MII Specification, Revision 1.2. All SMII ports use a common reference clock and SYNC signal. The SMII Data Interface exchanges data between the LXT9785/ LXT9785E and multiple Media Access Controllers (MACs). All signals are synchronous to the reference clock. One SYNC control stream is sourced by the MAC to the PHY. Both the transmit and receive data streams are segmented into boundaries delimited by the SYNC pulses. This interface is expected to drive up to 6 inches of trace lengths.
4.3.4.2
Source Synchronous-Serial Media Independent Interface
The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK, and RxSYNC. The transmit TxCLK and TxSYNC are sourced from the MAC to the PHY and referenced to the REFCLK input. The receive RxCLK and RxSYNC are sourced by the PHY to the MAC and in reference to the REFCLK.
4.3.5
Configuration Management Interface
The LXT9785/LXT9785E provides an MDIO Management Interface and a Hardware Control Interface (via the CFG pins) for device configuration and management. Mode control selection is provided via the MDDIS pin as shown in Table 9, "Intel(R) LXT9785/LXT9785E MDIO Control Interface Signals - PQFP" on page 41. When sectionalization (2x4) is selected, separate MDIO interfaces are enabled (see Figure 13 on page 127).
4.3.6
MII Isolate
In applications where the MII must be isolated from the bus, the RMII and the SMII/SS-SMII configurations can be three-stated using Register 0.10. On each individual port, Register bit 0.10 controls the isolation of the transmit and receive data signals for that port. Register bit 0.10 on ports 0 and 4 isolate the RxCLKn/TxCLKn and SYNC signals. When 1x8 sectionalization is selected, TxCLK0, TxSYNC0, RxCLK1, and RxSYNC1 are used for the clocking and synchronization interface. Port 4 controls the isolation of RxCLK0, RxCLK1, RxSYNC0, and RxSYNC1, and must be used to isolate the receive clock and synchronization interface. When 2x4 sectionalization is selected, TxCLK0, TxSNC0, RxCLK0, and TxCLK0 are used for Port 0 through Port 3 and TxCLK1, TxSYNC1, RxCLK1, and RxSYNC1 are used for Port 4 through Port 7. Port 0 must be isolated to isolate the receive clock and synchronization interface for Port 0 through Port 3. Port 4 must be isolated to isolate Port 4 through Port 7.
4.3.7
MDIO Management Interface
The LXT9785/LXT9785E supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT9785/LXT9785E. The MDIO interface consists of a
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physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. Additional registers allow for expanded functionality. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are completely disabled. The Hardware Control Interface provides primary configuration control. When MDDIS is Low, the MDIO port is enabled for both read and write operations and the Hardware Control Interface is not used. Note: The BGA15 package does not support the MDDIS pin. The timing for the MDIO Interface is shown in Table 79, "Intel(R) LXT9785/LXT9785E MDIO Timing Parameters" on page 197. MDIO read and write cycles are shown in Figure 9, "Intel(R) LXT9785/LXT9785E Management Interface Read Frame Structure" on page 122 and Figure 10, "Intel(R) LXT9785/LXT9785E Management Interface Write Frame Structure" on page 122. Figure 9. Intel(R) LXT9785/LXT9785E Management Interface Read Frame Structure
MDC
MDIO (Read)
High Z
32 "1"s Preamble
0 ST
1
1
0 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
Z
0
D15 D15D14 D14 D1 Data Read
D1 D0 Idle
Register Address
Turn Around
Write
Figure 10. Intel(R) LXT9785/LXT9785E Management Interface Write Frame Structure
MDC MDIO (Write)
Idle
32 "1"s Preamble
0 ST
1
0
1 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
1
0 Turn Around
D15
D14 Data
D1
D0 Idle
Register Address Write
The protocol allows one controller to communicate with multiple LXT9785/LXT9785E chips. Pins ADD_<4:0> determine the base address. Each port adds its port number to the base address to obtain its port address as shown in Figure 11. The BGA15 package uses a similar scheme where the ADD_[2:0] bits internally set to 0 and the ADD_[4:3] bits are used to select from four base addresses (0x00000b, 0x01000b, 0x10000b, or 0x11000b.
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Figure 11. Intel(R) LXT9785/LXT9785E Port Address Scheme
BASE ADD_<4:0> (example ADD_<4:0> = 4) LXT9785 LXT9785/9785E Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 ex. 4 ex. 5 ex. 6 ex. 7 ex. 8 ex. 9
PHY ADD_<4:0> (BASE+0) PHY ADD_<4:0> (BASE+1) PHY ADD_<4:0> (BASE+2) PHY ADD_<4:0> (BASE+3) PHY ADD_<4:0> (BASE+4) PHY ADD_<4:0> (BASE+5) PHY ADD_<4:0> (BASE+6) ex. 10
ex. 11
PHY ADD_<4:0> (BASE+7)
4.3.8
MII Sectionalization
When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function is unaffected and operates normally. Sectionalization is selected by pulling pin 176 (Section) High on the initial power-up sequence (refer to Figure 13). In applications that need sectionalization, such as 1x8 and 2x4 and have a single MDIO bus structure, it is necessary that the addressing scheme be contiguous. For example, the first eight ports are addressed 0-7, so the next four ports must be addressed 8-11. Note: The BGA15 package does not support the MII sectionalization feature.
4.3.9
MII Interrupts
The LXT9785/LXT9785E provides a single per-section interrupt pin that is available to all ports. Interrupt logic is shown in Figure 12. The LXT9785/LXT9785E also provides two dedicated interrupt registers for each port. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1 enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the device. Because it is a shared interrupt, there is no indication which port is requesting interrupt service (see Figure 12). There are five conditions that may cause an interrupt:
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* * * * *
Auto-negotiation complete. Speed status change. Duplex status change. Link status change. Isolate status change.
Figure 12. Intel(R) LXT9785/LXT9785E Interrupt Logic
Event X Enable Reg AND Event X Status Reg
Per Event Force Interrupt Interrupt Enable
. . .
OR AND
Per port
. . .
Port Combine Logic
Interrupt Pin
Interrupt (Event) Status Register is cleared on read. X = Any Interrupt capabi lity
4.3.10
Global Hardware Control Interface
The LXT9785/LXT9785E provides a Hardware Control Interface for applications where the MDIO is not desired. Refer to "Initialization" on page 126 for additional details.
4.3.11
FIFO Initial Fill Values
The FIFO initial fill value sets the number of bits required to be written into the FIFO before the process of reading the packet out of the FIFO is started. The read operation is aligned on nibble boundaries because the FIFO is one nibble wide. The read clock on the RMII and SMII interfaces may occur any time within the next available nibble. Therefore, the effective size of the FIFO is one nibble less than the selected size. Large initial fill FIFO settings alter both the data-path latency and the InterFrame Gap (IFG) output on the RMII and SMII interfaces. The latency values are increased or decreased depending on the number of bits the FIFO size is increased or decreased. The IFG may decrease up to twice the size of the initial fill FIFO setting. When the following three conditions are met, the IPG on the RMII and SMII interfaces may become nonexistent between packets, effectively concatenating the packets into one long corrupted packet:
* The frequency difference between the link partner and the local LXT9895 device exceed
200 ppm (the IEEE standard requirement).
* Jumbo packets (8192 byte packets or longer) are used. * Packets on the wire occur with minimum Inter-Packet Gap (IPG) of 96 bit times.
The concatenation of the packets is flagged by the MAC as a CRC error and possibly an oversized packet depending upon the length indication capabilities of the MAC. The possibility of packet concatenation can be minimized on the RMII interface by setting the initial fill FIFO Register bits 18.15:14 to 01. The FIFO setting bits should be set to 10 for the SMII interfaces.
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4.4
4.4.1
Operating Requirements
Power Requirements
The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). These inputs may be supplied from a single source although decoupling is required to each respective ground. The fiber VCCPECL supply can be connected to either 2.5 V or 3.3 V. A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The power supply may be either +2.5 V or +3.3 V. VCCIO should be supplied from the same power source used to supply the controller on the other side of the interface. Refer to Table 53, "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/- 5%)" on page 174, Table 54, "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%)" on page 175, and Table 55, "Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics - SD Pins" on page 175 for I/O characteristics. As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 34 on page 168. The power supplies should be brought up as close to the same time as possible. However, there are no specific timing requirements.
4.4.2
4.4.2.1
Clock/SYNC Requirements
Reference Clock
The LXT9785/LXT9785E requires a constant enabled reference clock (REFCLK). REFCLK's frequency must be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (that is, PLL-based) to minimize transmit jitter. Refer to Table 56, "Intel(R) LXT9785/LXT9785E Required Clock Characteristics" on page 175 for clock timing requirements. For applications that use a single 8-port sectionalization, REFCLK0 and REFCLK1 must always be tied together and to the source. In 2x4 applications, REFCLK0 and REFCLK1 are not tied together.
4.4.2.2
TxCLK Signal (SS-SMII only)
The LXT9785/LXT9785E requires a 125 MHz input transmit clock synchronous with TxDatan and frequency locked to REFCLK. See Figure 22 on page 141.
4.4.2.3
TxSYNC Signal (SMII/SS-SMII)
The LXT9785/LXT9785E requires a 12.5 MHz input pulse for SMII synchronization. See Figure 22 on page 141.
4.4.2.4
RxSYNC Signal (SS-SMII only)
The LXT9785/LXT9785E provides a 12.5 MHz output pulse synchronous with the RxDatan outputs. See Figure 23 on page 141.
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4.4.2.5
RxCLK Signal (SS-SMII only)
In SS-SMII mode, the LXT9785/LXT9785E provides a 125 MHz clock output in reference to the output RxDatan. RxCLK is referenced and synchronized to the REFCLK. See Figure 23 on page 141.
4.5
Initialization
When the LXT9785/LXT9785E is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 13 on page 127.
4.5.1
MDIO Control Mode
In the MDIO Control mode, the LXT9785/LXT9785E reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface.
4.5.2
Hardware Control Mode
In the Hardware Control Mode, the LXT9785/LXT9785E disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset, the LXT9785/LXT9785E reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control:
* Force network link to 100BASE-FX (Fiber). * Force network link operation to:
-- 100BASE-TX, Full-Duplex -- 100BASE-TX, Half-Duplex -- 10BASE-T, Full-Duplex -- 10BASE-T, Half-Duplex
* * * *
Allow auto-negotiation/parallel-detection. Auto/Manual MDIX enable/disable. Pause for full-duplex links operation. Global Output Slew Rate Control.
When the network link is forced to a specific configuration, the LXT9785/LXT9785E immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT9785/LXT9785E begins the auto-negotiation/ parallel-detection operation.
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Figure 13. Intel(R) LXT9785/LXT9785E Initialization Sequence
Power-up or Reset Read H/W Control Interface
Initialize MDIO Registers
MDIO Control Mode
Low
MDDIS Voltage Level?
Hardware Control Mode
High
Pass Control to MDIO Interface
Disable MDIO Writes
Software Reset?
Yes
Hardware Reset?
Yes
Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset
4.5.3
Power-Down Mode
The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible. The device can be put into a low-power state via Register 0 as well as a near-zero power state with the power down pin. When in power-down mode, the device is not capable of receiving or transmitting packets. The lowest power operation is achieved using the Global power-down pin, which is active High. This pin powers down every circuit in the device, including all clocks. All registers are unaltered and maintained when the Global PWRDWN pin is released. Note: The BGA15 package does not support the PWRDWN pin feature. Individual ports (software power down) can be powered down using Register bit 0.11. This bit powers down a significant portion of the port, but clocks to the register section remain active. This allows the management interface to remain active during register power-down. The power-down bit is active High.
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Note:
Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware power-down or link hold-off modes. The recovery times are specified in Table 80, "Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters" on page 198
4.5.3.1
Global (Hardware) Power Down
The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true:
* * * * *
4.5.3.2
All LXT9785/LXT9785E ports and the clock are shut down. All outputs are three-stated. All weak pad pull-up and pull-down resistors are disabled. The MDIO registers are not accessible. Configuration pins are read upon release of the PWRDWN pin, and registers are loaded with the current values of the hardware configuration pins.
Port (Software) Power Down
Individual port power-down control is provided by Register bit 0.11 in the respective port Control Registers (refer to Table 83, "Control Register (Address 0)" on page 200). During individual port power-down, the following conditions are true:
* * * * 4.5.4
The individual port is shut down. The MDIO registers remain accessible. Pull-up and pull-down resisters are not affected and the outputs are not three-stated. The register remains unchanged.
Reset
The LXT9785/LXT9785E provides both hardware and software resets. Configuration control of Auto-Negotiation, speed, and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12, 0.8, and 4.8:5 are read in from the pins (refer to Table 42, "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129 for pin settings, and Table 83, "Control Register (Address 0)" on page 200 and Table 87, "AutoNegotiation Advertisement Register (Address 4)" on page 204 for register bit definitions). During a software reset (Register bit 0.15 = 1), the bit settings are not re-read from the pins and revert back to the values that were read in during the last hardware reset. Any changes to pin values from the last hardware reset are not detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. All MII interface pins are disabled during a hardware reset and released to the bus on de-assertion of reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not affected.
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Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware reset. The recovery times are specified in Table 80, "Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters" on page 198
4.5.5
Hardware Configuration Settings
The LXT9785/LXT9785E provides a hardware option to set the initial device configuration. The hardware option uses three Global CFG pins that provide control for all ports (see Table 42).
Table 42. Intel(R) LXT9785/9785E Global Hardware Configuration Settings
Desired Mode AutoNeg Speed 10 Disabled 100 Duplex Half Full Half Full Half Full/Half Half Full/Half 1 Low Low Low Low High High High High CFG Pin Settings1 2 Low Low High High Low Low High High 3 Low High Low High Low High Low High 1 0 1 1 1 1 1 0.12 Resulting Register Bit Values 0.13 0 0.8 0 1 0 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 N/A Auto-Negotiation Advertisement 4.8 4.7 4.6 4.5
100 Enabled 10/100
1. Refer to Table 5, "Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - PQFP" on page 36 through Table 17, "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations" on page 50 Table 24, "Intel(R) LXT9785/LXT9785E RMII Signal Descriptions - BGA23" on page 82 through Table 36, "Intel(R) LXT9785/ LXT9785E Receive FIFO Depth Configurations" on page 97, and Table 39, "Intel(R) LXT9785 BGA15 Signal Descriptions" on page 109 for CFG pin assignments.
4.6
4.6.1
Link Establishment
Auto-Negotiation
The LXT9785/LXT9785E attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may also be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, referred to as a "page". All devices that support auto-negotiation must implement the "Base Page", defined by IEEE 802.3 (registers 4 and 5). The LXT9785/LXT9785E also supports the optional "Next Page" function (registers 7 and 8).
4.6.1.1
Base Page Exchange
By exchanging Base Pages, the LXT9785/LXT9785E and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds their highest common capabilities, exchange more pages, and agree on the operating state of the line.
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4.6.1.2
Manual Next Page Exchange
Additional information, exceeding that required by base page exchange, is also sent via "Next Pages." The LXT9785/LXT9785E fully supports the IEEE 802.3 method of negotiation via Next Page exchange. The Next Page exchange uses Register 7 to send information and Register 8 to receive it. Next Page exchange occurs only if both ends of the link partners advertise their ability to exchange Next Pages. A special mode has been added to make manual next page exchange easier for software. When Register 6 "page" is received, it stays set until read. This bit is cleared when a new negotiation occurs, preventing the user from reading an old value in Register 6 and assuming there is valid information in Registers 5 and 8. The page received bit is cleared upon reading the "Auto-Negotiation Expansion Register (Address 6)" on page 206.
4.6.1.3
Controlling Auto-Negotiation
The following steps are recommended when auto-negotiation is controlled by software:
* After power-up, power-down, or reset, the power-down recovery time, as specified in
Table 80, "Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters" on page 198, must be exhausted before proceeding.
* Set the auto-negotiation advertisement register bits in Register 4 as desired. * Enable auto-negotiation (set MDIO Register bit 0.12 = 1). * Enable or restart auto-negotiation as soon as possible after writing to Register 4 to ensure
proper operation.
4.6.1.4
Link Criteria
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked for approximately 50 ms. Link remains up unless the descrambler receives less than 12 consecutive idle symbols in any 2 ms period. This provides a robust operation, filtering out any small noise hits that may disrupt the link. MLT-3 idle waveforms, for short periods, meet all the criteria for 10BASE-T start delimiters. A working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However, the PHY will not bring up a permanent 10 Mbps link. According to the IEEE standard 10 Mbps link state machine, the last condition that must be met before 10 Mbps link can come up is a period of transmit and receive idle time. TXEN and RXDV are inactive at the same time. This ensures that link is not brought up in the middle of transmitting or receiving a packet. To ensure link establishment, Intel recommends no packet transmission into the MII interface until link is established. The IEEE Standard references this requirement in Section 14.2.3 State Diagrams, Figure 14-6-Link Integrity Test Function State Diagram and in Section 28.3.4 State Diagrams, Figure 28-17-NLP Receive Link Integrity Test State Diagram. These diagrams illustrate that while the PHY is in the Link Test Fail Extend state, the last state before Link Pass state) Packet receive activity (RD) and Transmit Activity (DO) must be idle (RD = idle * D0 = idle) for link to establish.
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4.6.1.5
Parallel Detection
In parallel with auto-negotiation, the LXT9785/LXT9785E also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device automatically reverts to the corresponding operating speed in half-duplex mode. Parallel detection allows the LXT9785/LXT9785E to communicate with devices that do not support autonegotiation. When parallel detection resolves a link, the link must be established in half-duplex mode. According to IEEE standards, the forced link partner cannot be configured to full-duplex. If the auto-negotiation link partner does not advertise half-duplex capability at the speed of the forced link partner, link is not established. The IEEE Standard prevents forced full-duplex-to-half-duplex link connections.
Figure 14. Intel(R) LXT9785/LXT9785E Auto-Negotiation Operation
Power-Up, Reset, Link Failure
Start Disable Auto-Negotiation 0.12 = 0
Check Value 0.12
0.12 = 1
Enable Auto-Neg/Parallel Detection
Go To Forced Settings
Attempt AutoNegotiation
Listen for 100TX Idle Symbols
Listen for 10T Link Pulses
Done
YES
Link Set?
NO
4.6.1.6
Reliable Link Establishment While Auto MDI/MDIX is Enabled in Forced Speed Mode
With auto MDI/MDIX hardware enabled, end users experience reliable link establishment under all settings of auto MDI/MDIX and speed between the LXT9785/LXT9785E and its link partners. As stated in the IEEE clauses 40.4.5.1 (Auto MDI/MDIX) and 28.3.2 (Parallel Detect), when ports are forced to 10 Mbps or 100 Mbps and auto MDI/MDIX is enabled, and the port is connected to a partner with auto-negotiation enabled, an undefined condition exists between the IEEE auto MDIX and Parallel Detect specifications. Link may not occur according to the IEEE specification. During this undefined condition, when the LXT9785/LXT9785E is set to 10 Mbps or 100 Mbps and auto MDI/MDIX is enabled, the LXT9785/LXT9785E and the link partner auto-negotiation processes are expected to be skewed enough to establish link in all but the rarest cases. Auto MDI/ MDIX is configured through hardware and software. If auto MDI/MDIX operation is desired in forced modes, disabling auto MDI/MDIX using the software programming can aid link establishment.
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4.7
Serial MII Operation
The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions:
* * * *
Conveys complete MII information between a 10/100 PHY and MAC with two pins per port. Allows a multi-port MAC/PHY communication with one system clock. Operates in both half and full-duplex. Supports per-packet switching between 10 Mbps and 100 Mbps data rates.
The Serial MII operates at 125 MHz using a global reference clock and frame synchronization signal (REFCLK and SYNC). Each port has an individual two-line data interface (TxDatan and RxDatan). All signals are synchronous to REFCLK. Table 43 summarizes the SMII signals. Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B coded data) and two status bits. When the port is operating at 100 Mbps, each word contains a new data byte. When the port is operating at 10 Mbps, each data byte is repeated 10 times. Table 43. Intel(R) LXT9785/LXT9785E SMII Signal Summary
Signal TxData SYNC RxData REFCLK To PHY PHY MAC MAC & PHY From MAC MAC PHY System Purpose Transmit data & control Synchronization Receive data & control Synchronization
1. Refer to Table 7, "Intel(R) LXT9785/LXT9785E SMII Specific Signal Descriptions - PQFP" on page 39 for detailed signal descriptions.
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Figure 15. Intel(R) LXT9785/LXT9785E Typical SMII Interface Diagram
Typical SMII Interface in a 16-Port System
SECTION
8
TxDatan SYNC0 RxDatan
LXT9785/9785E 8-Port Phy
8-Port Media Access Controller ( MAC)
Magnetics/Fiber Transceiver
8
MDIO0 MDC0 MDINT0 RefCLK0
RefCLK1
125 MHz Sourced Externally or from Switch ASIC
SYSTEM CLK
RefCLK0 RefCLK1 8
TxDatan SYNC0 RxDatan
LXT9785/9785E 8-Port Phy
8-Port Media Access Controller (MAC)
Magnetics/Fiber Transceiver
8
MDIO0 MDC0 MDINT0
SECTION
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Figure 16. Intel(R) LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram
Typical SMII Interface in a 24-Port System
8
TxDatan SYNC0
RefClk0
RefClk1
LXT9785/9785E 8-Port Phy
Magnetics/Fiber Transceiver
8
RxDatan
12-Port Media Access Controller ( MAC)
MDIO0 MDC0 MDINT0
SECTION
4
TxDatan SYNC0 RxDatan
MDIO0 MDC0 MDINT0 RefClk0 RefClk1
LXT9785/9785E 4-Port (sec) 4-Port (sec)
4
Magnetics/Fiber Transceiver
125 MHz Sourced Externally or from Switch ASIC 4 4
TxDatan SYNC1 RxDatan
MDINT1
VCC SECTION
12-Port Media Access Controller ( MAC)
MDIO1 MDC1 MDINT0 MDIO0 MDC0 8
LXT9785/9785E 8-Port Phy
Magnetics/Fiber Transceiver
TxData n SYNC0
8
RxData n
SECTION RefClk0 RefClk1
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Figure 17. Intel(R) LXT9785/LXT9785E 100 Mbps Serial MII Data Flow
Serial Data Stream To/From S0 S1 D0 D1 D2 MAC
Strip TX_EN & TX_ER Status Bits
2 Nibbles Tx/Rx Data D0 D1 D2 D3
4B/5B
2 Symbols Tx/Rx Data S0 S1 S2 S3 S4 To/From PMD Sublayer
D3 D4 D5 D6 D7
Insert CRS & RX_DV Status Bits
D0 D1 D2 D3
S0
S1
S2
S3
S4
4.7.1
SMII Reference Clock
The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always be synchronized to the REFCLK by the MAC and PHY. The LXT9785/LXT9785E samples these signals on the rising edge of the REFCLK.
4.7.2
TxSYNC Pulse (SMII/SS-SMII)
The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse signals the start of each new segment (see Figure 21 on page 140).
4.7.3
Transmit Data Stream
Transmit data and control information are signaled in ten- bit segments. In 100 Mbps mode, each segment contains a new byte of data. In 10 Mbps mode, the MAC must repeat a 10M serial word ten times on TxData. The LXT9785/LXT9785E may sample that serial word at any point. The TxSYNC pulse signals the start of a new segment as shown in Figure 18.
4.7.3.1
Transmit Enable
The MAC must assert the TxEN bit in each segment of TxData, and de-assert TxENn after the last segment of the packet.
4.7.3.2
Transmit Error
When the MAC asserts the TxER bit in 100BASE-X mode, the LXT9785/LXT9785E drives "H" symbols onto the network interface. TxER does not have any function in 10M operation.
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Figure 18. Intel(R) LXT9785/LXT9785E Serial MII Transmit Synchronization
CLOCK
TxSYNC
TX
TxER
TxEN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7 TxER
4.7.4
Receive Data Stream
Receive data and control information are signalled in ten-bit segments. In 100 Mbps mode, each segment contains a new byte of data. In 10 Mbps mode, each segment is repeated ten times (except for the CRS bit), and the MAC can sample any of the ten segments.
4.7.4.1
Carrier Sense
The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS bit is set in real time, even in 10 Mbps mode (all other bits are repeated in 10 sequential segments).
4.7.4.2
Receive Data Valid
The LXT9785/LXT9785E asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion timing changes depending on line operating speed:
* For 100BASE-TX and 100BASE-FX links, the RX_DV bit is asserted from the first nibble of
preamble to the last nibble of the data packet.
* For 10BASE-T links, the entire preamble is truncated. The RX_DV bit is asserted with the
first nibble of the Start-of-Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet.
4.7.4.3
Receive Error
When the LXT9785/LXT9785E receives an invalid symbol from the network in 100BASE-TX mode, it drives "0101" on the associated RxData signals.
4.7.4.4
Receive Status Encoding
The LXT9785/LXT9785E encodes status information onto the RxData line during IPG as seen in Table 44 on page 137. Status bit RxData<5> indicates the validity of the upper nibble (RxData<7:4> of the last byte of the previous frame). RxData and RX_DV are passed through the internal elasticity FIFO to smooth any clock rate differences between the recovered clock and the 125 MHz reference clock.
4.7.5
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret COL conditions using CRS and TxEN. CRS is unaffected by the transmit path.
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Figure 19. Intel(R) LXT9785/LXT9785E Serial MII Receive Synchronization
CLOCK
RxSYNC
RXD0 RXD1 Speed RXD2 Duplex RXD3 Link RXD4 J abber RXD5 Valid RXD6 FCE RXD7 RXD7
RX
CRS
RX_DV RXER
CRS
Table 44. Intel(R) LXT9785/LXT9785E RX Status Encoding Bit Definitions
Signal CRS RxDV RxER (RxData0) SPEED (RxData1) DUPLEX (RxData2) LINK (RxData3) JABBER (RxData4) VALID (RxData5) False Carrier (RxData6) RxData7 Definition Carrier Sense - identical to MII, except that it is not an asynchronous signal. Receive Data Valid - identical to MII. When RX_DV = 0, status information is transmitted to the MAC. When RX_DV = 1, received data is transmitted to the MAC. Inter-frame status bit RxData0 indicates whether or not the PHY detected an error somewhere in the previous frame. Inter-frame status bit RxData1 indicates port operating speed. Inter-frame status bit RxData2 indicates port duplex condition. Inter-frame status bit RxData3 indicates port link status. Inter-frame status bit RxData4 indicates port jabber status. Inter-frame status bit RxData5 conveys the validity of the upper nibble of the last byte of the previous frame Inter-frame status bit RxData6 indicates whether or not the PHY has detected a false carrier event. This bit is set to 1. 0 = Status Byte 1 = Valid Data Byte 0 = No Error 1 = Error 0 = 10 Mbps 1 = 100 Mbps 0 = Half-duplex 1 = Full-duplex 0 = Down 1 = Up 0 = OK 1 = Error 0 = Invalid 1 = Valid 0 = No FC detected 1 = FC detected 1 = Always
1. Both RxData0 and RxData5 bits are valid in the segment immediately following a frame, and remain valid until the first data segment of the next frame begins.
4.7.6
Source Synchronous-Serial Media Independent Interface
Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A new Source Synchronous-Serial Media Independent Interface (SS-SMII) definition has been added because of this requirement. To provide a source synchronous interface between the PHY and MAC, the PHY must drive the RxCLK and the RxSYNC signals to the MAC. Also, the MAC must drive the TxCLK and the TxSYNC signal to the PHY. The REFCLK is also needed to synchronize the data to the PHY's core clock domain. TxData is clocked in using TxCLK and then synchronized to REFCLK and transmitted to the twisted-pair. The RxData is synchronized to the RxCLK. See Figure 23 on page 141.
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Table 45. Intel(R) LXT9785/LXT9785E SS-SMII
Signal TxData TxCLK TxSYNC RxData RxCLK RxSYNC REFCLK To PHY PHY PHY MAC MAC MAC MAC From MAC MAC MAC PHY PHY PHY System Purpose Transmit data & control Transmit clock Synchronization pulses Receive data & control Receive clock Receive Synchronization Synchronization
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Figure 20. Intel(R) LXT9785/LXT9785E Typical SS-SMII Interface Diagram
Typical SS-SMII Interface in a 16-Port System
SECTION
8
TxDatan TxSYNC0 TxCLK0
LXT9785/9785E 8-Port Phy
8-Port Media Access Controller ( MAC)
Magnetics/Fiber Transceiver
8
RxDatan RxSYNC1 RxCLK1
MDIO0 MDC0 MDINT0
RefCLK0,1
125 MHz Sourced Externally or from Switch ASIC
SYS_CLK RefCLK0,1 TxDatan TxSYNC0 TxCLK0
LXT9785/9785E 8-Port Phy
8
8-Port Media Access Controller (MAC)
Magnetics/Fiber Transceiver
8
RxDatan RxSYNC1 RxCLK1
MDIO0 MDC0 MDINT0
SECTION
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Figure 21. Intel(R) LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram
Typical SS-SMII Interface in a 24-Port System
8
RefClk0
RefClk1
TxData n TxSYNC0 TxCLK0 RxData n RxSYNC1 RxCLK1
LXT9785/9785E 8-Port Phy
Magnetics/Fiber Transceiver
8
12-Port Media Access Controller ( MAC)
MDIO0 MDC0 MDINT0
SECTION
4
4
TxData n TxSYNC0 TxCLK0 RxData n RxSYNC0 RxCLK0
MDIO0 MDC0 MDINT0 RefClk0 RefClk1
4-port (sec) LXT9785/9785E 4-port (sec)
Magnetics/Fiber Transceiver
125 MHz Sourced Externally or from Switch ASIC 4
TxData n TxSYNC1 TxCLK1
4
RxData n RxSYNC1 RxCLK1
MDINT1 MDIO1 MDC1 MDINT0
VCC
12-Port Media Access Controller ( MAC)
SECTION
LXT9785/9785E 8-Port Phy
MDIO0 MDC0 8
Magnetics/Fiber Transceiver
TxData n TxSYNC0 TxCLK0
8
RxData n RxSYNC1 RxCLK1
SECTION
RefClk0 RefClk1
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Figure 22. Intel(R) LXT9785/LXT9785E SS-SMII Transmit Timing
TxCLK TxSYNC TxData TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER
TxCLK TxSYNC TxData TXER TXEN Frcerr Speed Dplx LINK Jabr TXER
All signals are synchronous to the clock
Figure 23. Intel(R) LXT9785/LXT9785E SS-SMII Receive Timing
RxCLK RxSYNC RxData CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS
RxCLK RxSYNC RxData CRS RXDV RXER Speed Dplx LINK Jabr UPnib FlsCar CRS
All signals are synchronous to the clock
4.8
RMII Operation
The LXT9785/LXT9785E provides an independent Reduced MII port for each network port. Each RMII uses four signals to pass received data to the MAC: RxDatan<1:0>, RxERn, and CRS_DVn (where n reflects the port number). Three signals are used to transmit data from the MAC: TxDatan_<1:0> and TxENn. Both receive and transmit signals are clocked by REFCLK. Data transmission across the RMII is implemented in di-bit pairs which equal a 4-bit wide nibble. Note: The BGA15 package does not support the RMII interface.
4.8.1
RMII Reference Clock
The LXT9785/LXT9785E requires a 50 MHz reference clock (REFCLK). The device samples the RMII input signals on the rising edge of REFCLK and drives RMII output signals on the falling edge.
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4.8.2
Transmit Enable
TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted after the last bit of the packet.
4.8.3
Carrier Sense & Data Valid
The LXT9785/LXT9785E asserts CRS_DVn when it detects activity on the line. However, RxDatan outputs zeros until the received data is decoded and available for transfer to the controller.
4.8.4
Receive Error
Whenever the LXT9785/LXT9785E receives an error symbol from the network, it asserts RxERn. When it detects a bad Start-of-Stream Delimiter (SSD) it drives a "10" jam pattern on the RxData pins to indicate a false carrier event.
4.8.5
Out-of-Band Signaling
The LXT9785/LXT9785E has the capability of encoding status information in the RxData stream during IPG. See "Monitoring Operations" on page 157 for details.
4.8.6
4B/5B Coding Operations
The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However, data is normally transmitted across the RMII interface in 2-bit nibblets or "di-bits". The LXT9785/ LXT9785E incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the 100BASE-X connection. Figure 24 shows the data conversion flow from nibbles to symbols. Table 46 on page 147 shows 4B/5B symbol coding (not all symbols are valid).
Figure 24. Intel(R) LXT9785/LXT9785E RMII Data Flow
Reduced MII Mode Data Flow
Parallel to Serial
+1 0 0 -1 0
D0 D1
D2 D3
Scramble
D0 D1 D2 D3
di-bit pairs Serial to Parallel 4-bit nibbles
4B/5B
S0
S1
S2
5-bit symbols
S3
S4
DeScramble
MLT3
Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1...
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Figure 25. Intel(R) LXT9785/LXT9785E Typical RMII Interface Diagram
Typical RMII Interface in a 16-Port System
8
SECTION
TxD0n TxD1n TxENn RxD0n RxD1n CRS_DVn RxERn
MDIO0 MDC0
8 8
LXT9785/9785E 8-Port Phy
8-Port Media Access Controller ( MAC)
8 8 8 8
Magnetics/Fiber Transceiver
MDINT0
RefClk0 RefClk1
50 Mhz Sourced Externally or from Switch ASIC
RefClk0 MDINT0 MDIO0
RefClk1
LXT9785/9785E 8-Port Phy
MDC0
8-Port Media Access Controller ( MAC)
8 8 8 8 8 8 8
TxD0 n TxD1n TxEN n RxD0 n RxD1n CRS_DV n RxERn
Magnetics/Fiber Transceiver
SECTION
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 26. Intel(R) LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram
Typical RMII Interface in a 24-Port System
8 8 8 8 8 8
RefClk0 RefClk1
LXT9785/9785E 8-Port Phy
TxD0n TxD1n TxENn RxD0n RxD1n CRS_DVn RxERn
MDIO0 MDC0 MDINT0 4 4 4 4 4 4 4
Magnetics/Fiber Transceiver
12-Port Media Access Controller ( MAC)
8
SECTION
TxD0n TxD1n TxENn RxD0n RxD1n CRS_DV n RxERn
MDIO0 MDC0 MDINT0 RefClk0
LXT9785/9785E 4-Port (sec) 4-Port (sec)
Magnetics/Fiber Transceiver
50 MHz Sourced Externally or from Switch ASIC
4 4 4 4 4 4 4
RefClk1
TxD0n TxD1n TxENn RxD0 n RxD1n CRS_DVn RxER n
MDINT1 MDIO1 MDC1 MDINT0 MDIO0 MDC0 8 8 8 8 8 8 8
VCC
12-Port Media Access Controller ( MAC)
SECTION
LXT9785/9785E 8-Port Phy
Magnetics/Fiber Transceiver
TxD0 n TxD1n TxEN n RxD0 n RxD1n CRS_DV n RxERn
SECTION RefClk0 RefClk1
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4.9
4.9.1
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT9785/LXT9785E transmits and receives 5-bit symbols across the network link. Figure 27 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT9785/LXT9785E sends out Idle symbols on the line. In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are de-scrambled and decoded, and sent across the RMII to the MAC. In 100BASE-FX mode, the LXT9785/LXT9785E transmits and receives NRZI signals across the LVPECL interface. An external 100BASE-FX transceiver module is required to complete the fiber connection. As shown in Figure 27, the MAC starts each transmission with a preamble pattern. As soon as the LXT9785/LXT9785E detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT9785/LXT9785E transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to transmitting Idle symbols.
Figure 27. Intel(R) LXT9785/LXT9785E 100BASE-X Frame Format
64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets)
P0
P1
P6
SFD
DA
DA
SA
SA
L1
L2
D0
D1
Dn
CRC
I0
IFG
Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD)
Start-of-Frame Delimiter (SFD)
Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD)
4.9.2
100BASE-X Protocol Sublayer Operations
In a 7-layer communications model, the LXT9785/LXT9785E is a Physical Layer 1 (PHY) device. The LXT9785/LXT9785E implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss the LXT9785/ LXT9785E operation from the reference model point of view.
4.9.2.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX and 100BASE-FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TxEN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function. 10T operation does not use the 4B/5B encoder.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.2.1.1
Preamble Handling
When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer continues to encode the remaining RMII data until TxEN is de-asserted (see Table 46 on page 147). It then returns to supplying IDLE symbols to the line driver. The PCS layer performs the opposite function in the receive direction by substituting two preamble nibbles for the SSD. Figure 28. Intel(R) LXT9785/LXT9785E Protocol Sublayers
MII Interface PCS Sublayer LXT9785
Encoder/Decoder Serializer/De-serializer
PMA Sublayer
Link/Carrier Detect
PMD Sublayer
LVPECL Interface
Scrambler/ De-scrambler Fiber Transceiver
100BASE-TX
100BASE-FX
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4.9.3
PMA Sublayer
The 100BASE-X PMA protocol uses the 4B/5B data encoding scheme to encode/decode the data streams. The coding scheme is shown in Table 46.
Table 46. 4B/5B Coding
Code Type 4B Code 3210 0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDLE undefined 0101 CONTROL 0101 undefined undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined undefined 1. 2. 3. 4. Name 0 1 2 3 4 5 6 7 8 9 A B C D E F I J
1 2
5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 1 1 1 11 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F
Interpretation
Idle. Used as inter stream fill code. Start-of-Stream Delimiter (SSD), part 1 of 2. Start-of-Stream Delimiter (SSD), part 2 of 2. End-of-Stream Delimiter (ESD), part 1 of 2. End-of-Stream Delimiter (ESD), part 2 of 2. Transmit Error. Used to force signaling errors. Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
K2 T3 R3 H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
4.9.3.1
Link
In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a robust link, filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps idle patterns will not bring up a 10 Mbps link. The LXT9785/LXT9785E reports link failure via the Register status bits (1.2, 17.10, and 19.4) and interrupt functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.
4.9.3.2
Link Failure Override
The LXT9785/LXT9785E normally transmits 100 Mbps data packets or Idle symbols only if it detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this function, allowing the LXT9785/LXT9785E to transmit data packets even when the link is down. This feature is provided as a diagnostic tool.
Note:
Auto-negotiation must be disabled to transmit data packets in the absence of link. If autonegotiation is enabled, the LXT9785/LXT9785E automatically begins transmitting FLP bursts if the link goes down.
4.9.3.3
Carrier Sense/Data Valid (RMII)
The LXT9785/LXT9785E asserts CRS_DV whenever the respective port receiver is in a non-idle state (as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not complete when CRS_DV is asserted, the LXT9785/LXT9785E outputs 00 on the RxData1:0 lines until the decoded data are available. When the line returns to an idle state, CRS_DV is de-asserted synchronously with respect to REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is deasserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals, CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.
4.9.3.4
Carrier Sense (SMII)
For 100BASE-TX and 100BASE-FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R/. In this event, receive error is indicated during the IPG until the next packet is received. For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of an End-of-Frame (EOF) marker.
4.9.3.5
Receive Data Valid (SMII)
The LXT9785/LXT9785E asserts the RX_DV bit when it receives a valid packet. However, RxData outputs zeros until the received data are decoded and available for transfer to the controller.
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4.9.3.6
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions.
4.9.3.6.1
Scrambler/Descrambler (100BASE-TX Only)
The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/descrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic and test support.
4.9.3.6.2
Baseline Wander Correction
The LXT9785/LXT9785E provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is, by definition, "unbalanced". This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander may cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT9785/LXT9785E baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths.
4.9.3.6.3
Polarity Correction
The LXT9785/LXT9785E automatically detects and corrects for the condition where the receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. Before the polarity switch occurs, every frame is inverted and causes RxER to assert. The specific number of RxER events observed depends on how many link pulses occur between packets.
4.9.3.7
Fiber PMD Sublayer
The LXT9785/LXT9785E provides an LVPECL interface for connection to an external 3.3 V or 5 V fiber-optic transceiver. (The external transceiver provides the PMD function for the optical medium.) The LXT9785/LXT9785E uses a 125 Mbaud NRZI format for the fiber interface, and does not support 10BASE-FL applications.
Note:
The BGA15 package does not support fiber interface.
4.9.3.7.1
Far End Fault Indications
The LXT9785/LXT9785E Signal Detect pins independently detect signal faults from the local fiber transceivers via the SD pins. The device also uses Register bit 1.4 to report Remote Fault indications received from its link partner. The device "ORs" both fault conditions to set bit 1.4. Register bit 1.4 is set once and clears when read.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
The far-end fault detection process in fiber operation requires idles to establish link. Link will not establish if a far-end fault pattern is the initial signal detected. Either fault condition causes the LXT9785/LXT9785E to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by Register bit 16.2.
* When Register bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785/
LXT9785E transmits far end fault code if fault conditions are detected by the Signal Detect pins. continues to transmit idle code and may or may not drop link depending on the setting for Register bit 16.14.
* When Register bit 16.2 = 0, the LXT9785/LXT9785E does not transmit far end fault code. It
The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones's followed by a single "0" and is repeated until the Far End Fault condition is removed.
4.10
10 Mbps Operation
The LXT9785/LXT9785E operates as a standard 10BASE-T transceiver and supports all the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT9785/LXT9785E transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the device sends out link pulses on the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT9785/LXT9785E and sent across the MII to the MAC. Note: The LXT9785/LXT9785E does not support fiber connections at 10 Mbps.
4.10.1
Preamble Handling
The LXT9785/9785E offers two options for preamble handling, which are selected by Register bit 16.5. In 10BASE-T mode, when Register bit 16.5 = 0, the device strips the preamble off the received packets. In RMII and the SMII modes, the CRS signal is asserted based upon receive activity. In the SMII modes, Out-of-Band (OOB) signaling is present until the SFD is output. The DV signal is initially asserted in the frame that the SFD is output. In RMII mode, zeros are output after receive activity is detected until the SFD is output. The packet is output following the SFD. When Register bit 16.5 = 1 in 10BASE-T mode, the LXT9785/LXT9785E passes the preamble through the RMII and the SMII interfaces. In RMII and the SMII modes, the CRS signal is asserted based upon receive activity. In the SMII modes, OOB signaling is continued until preamble is available from the receive FIFO. After the preamble, the SFD is output with the initial assertion of the DV signal. The RMII interface outputs zeros after receive activity is detected until preamble is available from the FIFO. The number of zero nibbles output before preamble is based upon the FIFO initial fill settings (Register bits 18.15:14). The preamble is followed by the SFD and the packet body. Register bit 16.5 has no effect in 100 Mbps operation.
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4.10.2
Dribble Bits
The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the RMII. If five through seven dribble bits are received, the second nibble is not sent onto the RMII bus.
4.10.3
Link Test
The LXT9785/LXT9785E always transmits link pulses in 10T mode. When enabled, the link test function monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If link pulses stop, the data transmission is disabled. If the link test function is disabled, the LXT9785/LXT9785E transmits to the connection regardless of detected link pulses. The link test function is disabled by setting Register bit 16.14 = 1.
4.10.3.1
Link Failure
Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT9785/LXT9785E returns to the auto-negotiation phase if autonegotiation is enabled.
4.10.4
Jabber
If a transmission exceeds the jabber timer, the LXT9785/LXT9785E disables the transmit and loopback functions and the Collision Status bit (Register bit 17.11) is set regardless of duplex. The jabber timer, according to the IEEE standard, must be between 20 ms to 150 ms. The RMII does not include a Jabber pin, but the MAC may read Register 1 to determine jabber status. The LXT9785/LXT9785E automatically exits jabber mode after the unjab time expires. This function is disabled by setting Register bit 16.10 = 1.
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4.11
DTE Discovery Process
The DTE discovery process is port dependent and must be enabled through software. The process is implemented as a next page option to the auto-negotiation flow. When the process is enabled, manual control of auto-negotiation next pages is not allowed. This feature applies to the LXT9785E transceiver only. The process depends upon an IP phone, or any other DTE capable of being powered remotely, having a specific filter that passes NLPs and FLPs. This filter should be non-polarized to insure that the latest status of Auto-MDIX operation does not effect operation. This filter attenuates 100 Mbps MLT3 signals and 10 Mbps Manchester-encoded signals, and must be bypassed when power is applied to the IP phone. Figure 29 shows a typical IP telephone system connection.
Figure 29. Typical IP Telephone System Connection
VoIP-Enabled Switch
SD Pr oCurve Switch 2424M
HP J4122B
Module Status Self Test Console Power Fault Reset Clear Act Fdx 100 Mode Select 7X 8X 9X 10X 11X 12X 1 7 2 8 3 4 5 6 13 14 1 5 16 17 18 19 20 2 1 22 23 24 Link Mode 9 10 11 12 Link Mode 1X 2X 3X 4X 5X 6X
10/100Base -T Ports 13X 14X 15X 16X 17X 18X
19X
20X
21X
22X
23X
24X
Power cable Power and data over Category 5 cable
Power Outlet UPS/ Generator Power cable
12 45 78 * 8
3 6 9 #
IP Telephone
Data only over Category 5 cable
Computer
Power Outlet
4.11.1
Definitions
The following terms are used throughout the DTE discovery sections: Negotiation Process: System: Link Partner: DTE: Standard Link Partner: Remote-Power DTE: Discovery: This includes auto-negotiation and parallel detection processes The switch system using the LXT9785E for DTE Discovery A device connected to the LXT9785E through twisted pair cables Data Terminal Equipment; any end-of-link partner A link partner that is not requiring power over a Category 5 cable; typically a PC Data Terminal Equipment requiring power over a Category 5 cable; typically an IP telephone The process of identifying the type of link partner present
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4.11.2
Interaction between Processor, MAC, and PHY
The state machines that control the mechanics of the Discovery process reside within the LXT9785E device. However, control of the power supply and overall system control reside in the system processor. The processor communicates with the power supply unit (PSU) and switches it on and off dependant on the data that is supplied by the PHY. The PHY register data is read by the MAC using the MDIO interface. The required control bits are contained in the PHY device register map and are discussed in detail in the section labeled "Management Interface and Control" on page 153.
Note:
The details of the processor/MAC interface and the processor/PSU interface are implementation specific and therefore are out of the scope of this specification. The following is an overview of the system control for a successful Remote-Power DTE discovery: 1. The discovery process is enabled by the DTE Discovery Process Enable (Dis_EN) Register bit 27.6 and the Auto-Negotiation Enable Register bit 0.12. Writing Register bit 27.6 immediately affects the Auto-Negotiation Base Page. If already enabled, auto-negotiation should be restarted after this bit is written to ensure proper operation. Register bit 4.15 is used for manual control of auto-negotiation next pages and should be left in the default state (cleared). 2. The LXT9785E PHY then tests to see if a Remote-Power DTE is present as the link partner. If a Remote-Power DTE is found, the Power Enable (Power_EN) Register bit 27.4 is set. The processor polls this signal via the MAC. 3. Upon detecting a Remote-Power DTE, the processor instructs the power supply to switch on. Once power has been applied to the DTE, normal negotiation takes place. The processor must enable the required negotiation process by restarting auto-negotiation, or by setting forced speed mode after power has been applied. The processor must poll the link-up Register bit 1.2 for the corresponding LXT9785E port, or the link status change interrupt, to ensure that the link has been established. 4. A time-out must be connected with this feature so that if link is not established within a predetermined time period (system dependant), the processor instructs the power supply to switch off. If link is not established prior to the expiration of the "link fail inhibit timer", the LXT9785E restarts negotiation with DTE detection if auto-negotiation mode was used to establish link with the phone, and the DTE process is still enabled. The LXT9785E restarts negotiation without DTE detection if either forced speed mode is used to establish link with the phone, or the DTE process is disabled. 5. If power is applied and link is established, the system must still poll the Link Status Register bit 1.2 for the corresponding LXT9785E port or the link status change interrupt. This is required since link status is the only way to know when the Remote-Power DTE is removed or unplugged. On seeing the Link_Down condition, the processor instructs the power supply to switch off, and the DTE Discovery begins again or is disabled.
4.11.3
Management Interface and Control
The management and control of the DTE discovery process is via the MDIO port. Each port on the LXT9785E is capable of running the discovery process, thus each port is independently controlled. This is achieved by each port having a dedicated set of control and status bits. These bits are found in Register 27 as follows:
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DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN) R/W Default value = 0: Disabled. Register bit 27.6 controls the operation of the process. The discovery process is disabled when Register bit 27.6 = 0, and enabled when Register bit 27.6 = 1. The MAC controller sets Register bit 27.6 to a 1 when a port search for a DTE requiring power is desired. Once set, Register bit 27.6 remains = 1 until the MAC clears it, either by directly clearing it or by resetting the PHY. This allows the discovery process to continue to function if unsuccessful in detecting a DTE, without being continually re-enabled by the MAC. If Register bit 27.6 is set after link is established, no action is taken until after the link goes down. POWER ENABLE - Register Bit 27.4 (Power_EN) R Default value = 0: No Remote-Power DTE found. Register bit 27.4 contains the result of the discovery process. When Register bit 27.4 = 0, the discovery process has not found Remote-Power DTE, and when Register bit 27.4 = 1, the discovery process has potentially found a DTE requiring power. This indicates power should be applied to the Category 5 cable. Register bit 27.4 is polled by the MAC during the discovery process, and is cleared when the PHY is reset, when auto-negotiation is restarted, or when autonegotiation is disabled. In the event of a discovery process being interrupted due to detection of an already powered link partner (auto-negotiation completion or Parallel Detection), Register bit 27.4 = 0. STANDARD LINK PARTNER DETECTED - Register Bit 27.3 (SLP_Det) R/W Clear on Read Default value = 0: No link partner found. When Register bit 27.3 = 1, a standard link partner has been detected by the LXT9785E (NLPs, MLT3 data, FLPs without next page support, or FLPs with non-matching next pages). This indicates power should not be applied to the Category 5 cable. When Register bit 27.3 = 0, other bits are checked to determine overall status of the link partner. Register bit 27.3 is cleared on read, or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled. LINK FAIL TIMEOUT - Register Bit 27.2 (LFIT Expired) R/W Clear on Read Default value = 0 (Link Fail Inhibit timer has expired without establishment of link with a standard link partner). Valid only when Standard Link Partner Detected Register bit 27.3 = 1. Register bit 27.2 is set if link is not established prior to the Link Fail Inhibit Timer expiring. This indicates that the Discovery process has restarted and the Standard Link Partner Detected Register bit may no longer be valid. Register bit 27.2 is cleared on read, or DTE discovery is disabled, link is established, or auto-negotiation is either restarted or disabled.
4.11.4
DTE Discovery Process Flow
The following section describes the DTE Discovery process.See Figure 30, "Intel(R) LXT9785E Negotiation Flow Chart" on page 156 for a flow chart of the discovery process.When DTE Discovery (27.6) and auto-negotiation (0.12) are enabled (auto-negotiation mode is required), the LXT9785E transmits the auto-negotiation base page with the next page ability bit set ("AutoNegotiation Advertisement Register (Address 4)" on page 204). System software polls Register 27 to determine if or when a Remote-Power DTE is detected. The receiver monitors the line to determine if NLPs, MLT3 data, or FLP bursts are being received. If the receive activity is FLP bursts, the status of the next page ability bit is checked. If the detected "link partner" also supports next page, then the LXT9785E transmits out the next page sequence
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associated with message code #5 (Organizationally Unique Identifier (OUI) Tag Code). The definition for the next pages to be sent out for this message code include some user-defined code values. These values are loaded with randomly created data from an internal LSFR that is free running and seeded with the PHY address of the LXT9785E port. The Next Pages are hard coded in the logic (the LXT9785E ignores any data written into Register 7) and are outlined in Table 47. The receiver monitors the next pages to determine that the exact next page data (especially the random data) transmitted is received. As soon as the first non-matching next page is detected, the DTE Discovery process is stopped and the base page is used to determine the capability options. The Power-Enable Register bit 27.4 is set when a Remote-Power DTE is detected as the link partner, and the last next page is repeatedly transmitted until software restarts the required negotiation process (auto-negotiation or forced-speed mode). The software should be written so that the negotiation is not restarted until the DTE has been powered up over the Category 5 cable. The Power-Enable Register bit 27.4 is cleared upon restarting or disabling auto-negotiation (selecting forced mode). The system must be able to detect over-current conditions and be capable of disabling power in case the link partner is not a RemotePower DTE. Some examples of devices that would mistakenly set Power-Enable Register bit 27.4 are a token-ring balun and a loopback cable. Once link partner power has been stabilized and sufficient time has passed for the link partner to initialize, the auto-negotiation process may be restarted. The negotiation process establishes link if a compatible mode exists between the LXT9785E and the link partner. If a compatible mode does not exist (not compatible or not established within the Link Fail Inhibit Timer period), the LXT9785E either restarts auto-negotiation/DTE discovery (discovery is enabled (27.6=1) and auto-negotiation is enabled (0.12 = 1)), or normal negotiation (discovery is disabled (27.6=0) and auto-negotiation is enabled (0.12 = 1)), or either 10 Mbps or 100 Mbps forced-mode operation (auto-negotiation is disabled (0.12 = 0)). The software must detect this non-link state and disable power. Table 47. Next Page Message #5 Code Word Definitions
Next Page Encoding OUI Tagged Message User Page 1 User Page 2 User Page 3 User Page 4 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1
a a a a a
1 0 0 0 0
0 0 0 0 0
t t t t t
0
0
0
0
0
0
0 2.0
0 2.1
1 2.2
0 2.3
1 2.4
3.10 3.11 3.12 3.13 3.14 3.15 2.5 0 L.10 2.6 0 L.9 2.7 L.8 L.8 2.8 L.7 L.7 2.9 L.6 L.6
2.10 2.11 2.12 2.13 2.14 2.15 L.5 L.5 L.4 L.4 L.3 L.3 L.2 L.2 L.1 L.1 L.0 L.0
1. a is the acknowledge bit; t is the toggle bit; L is the LFSR
4.11.5
DTE Discovery Behavior
The device behavior checks the comparison bit after each next page is successfully autonegotiated. If the first next page or any subsequent next page does not match, the DTE Discovery process transmits one last null page with the next page bit cleared to stop the DTE Discovery
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process. If each page is successfully auto-negotiated (it matches the transmitted page), DTE Discovery completes as previously described. The five Next Pages consist of a message page and four user pages. Figure 30. Intel(R) LXT9785E Negotiation Flow Chart
Start Power Up or Link Down 1.2 = 0 and Dis_EN 27.6 = 0 or Link Down 1.2 = 0 and Forced Mode
Assumptions: Auto-Negotiation/Forced Speed Set by Pins Advertisement Requirements Set by Pins
Default Mode Transmit based upon hardware configuration FLP, NLP or IDLE Symbols LFIT Expired 27.2 = 1 Dis_EN 27.6 = 0 FLP Detected Software Intervention Auto-negotiation 0.12 = 1 (if needed) Power_EN 27.6 = 1
LFIT Expired 27.2 = 1 Link Fail Timeout = 1 Dis_EN Not Set 27.6 = 0
NLPs or IDLE Symbols Detected
Link Down 1.2 = 0 and Dis_EN 27.6 = 1 and Auto-Neg 0.12 = 1
Discovery Base Transmit FLPs Base Page (Register 4) with Next Page 4.15 = 1
NLPs or IDLE Symbols Detected LFIT Expired 27.2 = 1 Dis_EN 27.6 = 1
Parallel Detection Determine Compatibility on Speed and Duplex Check Advertisement
FLP Detected LFIT Expired 27.2 = 1 Dis_EN 27.6 = 1 No
Auto Negotiation Determine Compatibility Options
No
Next Page Set?
Yes Yes AutoNegotiation?
Nonmatching DTE Discovery NP Received No
Next Page Transmission Use Random Data for User Defined Bits as Code
Compatibility Power Applied
Compatibility
Next Pages Received Power On Wait State for Proper Power Assertiion Set Mode Restart Auto-Negotiation or DTE Discovered Transmit Last Page Continuously Power_EN 27.4 = 1 Software Intervention Software Polled Power_EN 27.4 = 1 Turn On Power Supply Force Speed
Pages = Code Transmitted?
Yes
Link Up
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4.12
4.12.1
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation may be monitored as follows:
* Bits 1.2 and 17.10 = 1 once the link is established. * Additional bits in Register 1 (refer to Table 84, "Status Register (Address 1)" on page 201) and
Register 17 (refer to Table 93, "Quick Status Register (Address 17, Hex 11)" on page 209) can be used to determine the link operating conditions and status.
4.12.2
Per-Port LED Driver Functions
The LXT9785/LXT9785E incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3).
Note:
The BGA15 package only supports two LEDs per port (LEDn_1 and LEDn_2). On power up, all the LEDs lights up for approximately one second after reset de-asserts. Each LED may be programmed to one of several different display modes using the LED Configuration Register. Each per-port LED may be programmed (refer to Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213) to indicate one of the following conditions:
* * * * * * *
Operating Speed Transmit Activity Receive Activity Collision Condition Link Status Duplex Mode Isolate Condition
The LEDs can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
* If Link is down, LED is off. * If Link is up, LED is on. * If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits
20.3:2 and continues to blink as long as activity is present. The LED driver pins are open drain circuits (10mA max current rating). Refer to "LED Circuit" on page 167 under the Application Information Section for LED circuit design details. The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see Table 96, "LED Configuration Register (Address 20, Hex 14)" on page 213). When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires, the stretch timer is reset and the stretch time extended.
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When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer. When the stretch timer expires, the edge detector is reset so that a long event causes another pulse to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED driver to remain asserted. Figure 31 on page 158 shows how the stretch operation functions. Figure 31. Intel(R) LXT9785/LXT9785E LED Pulse Stretching
Event
LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active L ow.
4.12.3
Out-of-Band Signaling
The LXT9785/LXT9785E provides an out-of-band signaling option to transfer status information across the RMII receive interface. This feature is enabled when Register bit 25.0 = 1 and uses the RxData(1:0) data bus during the Inter-Packet Gap (IPG) time as shown in Figure 32. Out-of-Band signaling is disabled when Isolate mode is enabled by setting Register 0.10.
Note:
The BGA15 package does not support Out-of-Band Signaling nor the RMII interface. The two status bits transferred across the RxData bus are software selectable via Register 25 (see Table 98, "RMII Out-of-Band Signaling Register (Address 25, Hex 19)" on page 215). In normal operation, the LXT9785/LXT9785E stuffs the RxData bus with zeros during the IPG. A software-selectable bit enables the RMII out-of-band signaling feature. Once this bit is set, the LXT9785/LXT9785E replaces the zeros with selected status bits during the IPG.
Figure 32. Intel(R) LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling
REFCLK
CRS_DV
RXD(1)
sta tus 1
status 1
0s
data
data
data
data
status 1
status 1
status 1
status 1
status 1
RXD(0)
sta tus 0
status 0
0s
data
data
data
data
status 0
status 0
status 0
status 0
status 0
1. When network activity is detected, the LXT9785/LXT9785E asserts CRS_DV asynchronously with respect to REFCLK. 2. After CRS_DV is asserted, the LXT9785/LXT9785E zero-stuffs the RxData bits until the received data has been processed through the FIFO. 3. When network activity ceases, the LXT9785/LXT9785E de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV toggles until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, LXT9785/LXT9785E drives the status bits selected by the Out-of-Band Signaling Register (refer to Table 98, "RMII Out-of-Band Signaling Register (Address 25, Hex 19)" on page 215) on the
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The LXT9785/LXT9785E includes an IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible.
4.12.4
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TCK and TRST). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up and the TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.
4.12.5
State Machine
The TAP controller is a 16-state machine driven by the TCK and TMS pins. Upon reset, the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are High for five TCK periods.
4.12.6
Instruction Register
The IDCODE instruction is always invoked after the state machine resets. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in Table 49.
4.12.7
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 48. Refer to the Identification Information section in the LXT9785/LXT9785E Specification Update (document number 249357) for the JTAG ID numbers.
Table 48. BSR Mode of Operation
Mode 1 2 3 4 Description Capture Shift Update System Function
Table 49. Supported JTAG Instructions
Name EXTEST IDCODE SAMPLE High Z Clamp BYPASS Code 0000 Hex FFFE Hex FFF8 Hex FFCF Hex FFEF Hex FFFF Hex Description External Test ID Code Inspection Sample Boundary Force Float Clamp Bypass Scan Data Register BSR ID REG BSR Bypass BSR Bypass
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4.13
Cable Diagnostics Overview
Debugging cable problems increases the overall cost of owning and operating a local area network. Cable Diagnostic tools were incorporated into the LXT9785 device to help customers debug network cable problems. The Cable Diagnostic tools provide the ability to detect severe cable problems, such as open and short circuits, and determine the distance to the discontinuity.
4.13.1
Features
The following are three cases to consider for Cable Diagnostics:
* Distance to a short circuit between wires of a single twisted-pair * An open circuit * Detection of an improperly terminated cable by the link partner.
An improperly terminated cable will not meet IEEE 802.3 return loss requirements. Register 29 has been added to control cable testing and report cable testing results. Cable Diagnostics provides a method to determine the distance to opens and shorts when the link partner is inactive on the twisted-pair under test. The cable tests produce undefined results if the link partner is transmitting signals. Implementation methods may vary depending upon the system use requirements of Cable Diagnostics.
4.13.2
Operation
Cable Diagnostics utilizes the PHY transmit drivers and receivers to test a single twisted-pair. A transmit pulse is driven down the twisted-pair under test and the reflected signal is analyzed. Link partners transmitting NLP, FLP, MLT3, or other TDR pulses may interfere with the ability of the LXT9785 to properly analyze the reflected Cable Diagnostic pulse. Implementation algorithms must take these potential situations into consideration.
4.13.2.1
Short and Long Cable Testing Requirements
Implementing Cable Diagnostic tests, by enabling short and long cable tests sequentially, allows more accurate measurements to a detected fault. Both tests are necessary to reach full precision. The short and long cable tests can be run by writing 0x7400h and 0x6C00h to Register 29, respectively. See Section 4.13.4, "Basic Implementation" on page 161 for implementation details.
4.13.2.2
Precision
Cable Diagnostics estimates the distance to a fault up to 150 m. Category 5 or better cable produces the most accurate test results. Less than Category 5 cable may produce less accurate results on long cable lengths. Cable Diagnostics returns the distance to the closest fault, if a fault is present. Cable Diagnostic tests report the distance to a cable fault based on the velocity of signal propagation, which is used to determine the electrical length to the fault. The electrical length may vary slightly from the physical cable length. The measurement accuracy may vary by +/- 2 m. The following basic equation is used to calculate the distance to a fault: Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16
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4.13.3
Implementation Considerations
Before performing Cable Diagnostics, the twisted-pair to be tested may be verified to be inactive. All applicable link configurations should be attempted. Cable Diagnostic tests may be started if the attempts indicate no link partners are active. If link partners are detected, additional tests and decisions as to next steps may need to be implemented in the cable testing algorithm to ensure the most accurate results. Intel recommends that a 100BASE-TX link be attempted with MDI and MDIX enabled sequentially, prior to performing Cable Diagnostic testing, to determine if a 100BASE-TX-only link partner is present. If a link partner is in forced 100BASE-TX operation, transmitting MLT3, the Cable Diagnostic test result will be undefined due to the interference MLT3 causes in attempting to process the reflected Cable Diagnostic pulse. Auto MDI/MDIX on the link partner should be accounted for in deriving the cable testing algorithm. Intel recommends auto MDI/MDIX be disabled when running the cable tests. The transmit and receive twisted-pairs must be tested one at a time with both short and long cable test suites. The MDI/MDIX control bits in Table 99, "Trim Enable Register (Address 27, Hex 1B)" on page 216 can be used to select the twisted-pair to be tested. This requirement creates a minimum of four test permutations that must be completed to determine if the fault exists, the distance to the fault. If Cable Diagnostics testing is completed using a powered down LXT9785 device as the link partner, specific results can be expected. The results will indicate an open connection when the PWRDWN hardware configuration pin is used. These power-down methods disable the internal termination resistors to create a high impedance connection equivalent to an open circuit. If Transmit Disable (Register bit 16.13) or software controlled Power-Down (Register bit 0.11) is used, the powered down device transmit logic will look like an open circuit and the receive circuit will look like a 100 terminated connection. The Transmit Disable bit and the software PowerDown bit disable the transmit circuit but do not affect the receive circuit. The result of Cable Diagnostic tests using an IP Phone indicate an open or a short fault at a gross approximation of the distance to the IP Phone. The termination resistors are not powered and do not create a proper termination. The filter circuit used by some manufacturers adversely affects the test results. Transmission and reception of packets is disabled when Cable Diagnostics is enabled. Internal loopback must be disabled for Cable Diagnostics to operate properly. Internal loopback disables the analog interface.
4.13.4
Basic Implementation
Register 29 is used to control and report the Cable Diagnostics test results. The function tests one pair of the twisted-pair cable at a time. The basic process flow is described as follows (see Table 100, "Cable Diagnostics Register (Address 29, Hex 1D)" on page 217 for Register 29 bit definitions): 1. Disable auto-negotiation by clearing Register bit 0.12, set to MDI by clearing Register bits 27.9:8, and ensure internal loopback is disabled, Register bit 0.14 = 0. 2. Write 0x7400h to Register 29. Setting these bits places the device in short cable Cable Diagnostics mode and forces link to drop. The device waits a specific amount of time (1.2 s to 1.5 s) to ensure link drops on any connected link partner, and initiates the Cable Diagnostics test on the selected twisted-pair.
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3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain a value used to determine if a cable fault was found and the distance to that fault. A value of 0xFFh indicates no fault was found. Any other value indicates a fault was found, that value should be stored for later use. 4. Write 0x6C00h to Register 29. Setting these bits places the device in long cable Cable Diagnostics mode. 5. Poll Register bit 29.9. When set, record the value of Register bits 29.7:0 if a fault is found. 6. If a fault is present, a calculation is used to determine the distance to the fault. Insert the smallest value recorded from Register bits 29.7:0 in steps 3 and 5 above into the following formula: Distance_to_Fault = (Reg29[7:0] - 3.5) / 1.16 Register bit 29.8 is set if the fault is detected as a short circuit and is cleared if the fault is detected as an open circuit. Register bits 29.12:11 are cleared when read and are cleared during the same read cycle when Register bit 29.9 is read, indicating a fault condition exists. 7. Normal PHY operation can be resumed by writing 0x4000h to Register 29 or by software or hardware reset. The test suite can be run again by resuming at step 2 above.
4.14
Link Hold-Off Overview
The PHY link is established as soon as the system platform powers-up. In many cases, the system platform is not capable of supporting network operation until configuration firmware is loaded. It is desirable in such cases to prevent the PHY from establishing a link until the system platform is fully configured and ready for network operation. Link Hold-Off was incorporated into the LXT9785 device to satisfy these requirements. Enabling Link Hold-Off disables the PHY Link capability until the system platform is fully capable of supporting network operation. The feature is enabled by hardware control at power-up or software control during normal operation.
4.14.1
Features
Link Hold-Off prevents the LXT9785 from establishing a link by disabling the analog transmit and receive capability. The digital capabilities of the PHY are unaffected including register access and LED operation. Link Hold-Off can be enabled by an external hardware pin for all ports or by software register access for individual ports. When Link Hold-Off is enabled, the transmitter and receiver on the selected ports are forced into software power-down mode (see Section 4.5.3, "Power-Down Mode" on page 127) to block signal activity from establishing a link and passing packets through the PHY. The hardware enabled Link Hold-Off is controlled by the LINKHOLD pin. Internal pull-down resistors hold the pin in the inactive state. Connecting a 5k pull-up resistor to the pin enables the feature at power-up reset or external hardware pin Reset. Once a PHY port is programmed as desired, clearing Register bit 0.11 will re-enable that port. Each port must be individually reenabled. When a port is software reset, by setting Register 0.15, the state of the hardware configuration pin captured by the last hardware or power-up reset determines the default register values for the specific function for that port. Link Hold-Off, once enabled by hardware configuration, is reenabled on a port by issuing a software reset for that port. It is not necessary to reset the entire PHY or switch system to re-enable Link Hold-Off.
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Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or clearing Register bit 0.11, the power-down bit, during normal operation. It is not required to have previously enabled Link Hold-Off by hardware configuration. Link Hold-Off is disabled if the external pin MDDIS is active. The MDDIS pin disables the MDIO interface required to re-enable normal transmit and receive link operation. MDDIS is intended to disable the MDIO management interface for unmanaged applications. Internal loopback circuitry is unaffected in Link Hold-Off mode.
4.14.2
Operation
Link Hold-Off is implemented in one of the following two ways:
* Using a hardware pin at power-up or hardware reset * Using software control through the MII Management (MDC/MDIO) interface.
Link Hold-Off use by an external hardware pin is as follows: 1. Pull the LINKHOLD pin High with a pull-up resistor (approximately 5 k Ohms). 2. Power up the system or drive the reset pin active. 3. All ports are link disabled. 4. Program all ports to the desired configuration. 5. Clear Register Bit 0.11, power-down for each individual port. 6. Normal operation resumes on each port after Register bit 0.11 is cleared (see Table 83 for the recovery time). Link Hold-Off is enabled on a per port basis by software control using the following two methods: Method One: This method requires that Link Hold-Off is enabled by the LINKHOLD pin during the last powerup or hardware reset. 1. Set Register bit 0.15 to reset and re-enable Link Hold-Off for the desired port. 2. Program the PHY to the desired configuration. 3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off. 4. Normal operation resumes. Method Two: This method enables Link Hold-Off regardless of the LINKHOLD hardware configuration state. 1. Set Register bit 0.11(power-down) to enable Link Hold-Off for the desired port. 2. Program the PHY to the desired configuration. 3. Clear Register bit 0.11 (power-down) to disable Link Hold-Off. 4. Normal operation resumes. Note: High is defined by the IO voltage supply level selected (2.5V or 3.3V).
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5.0
5.1
Application Information
Design Recommendations
The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from the LXT9785/LXT9785E, attention to detail and good design practices are required. Refer to the LXT9785 Design and Layout Guide application note for detailed design and layout information.
5.2
General Design Guidelines
Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency switching noise can be reduced, and its effects eliminated, by following these simple guidelines throughout the design:
* Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC
or ground plane that is not located adjacent to the signal layer.
* Use ample bulk and decoupling capacitors throughout the design (a value of 0.01F is
recommended for decoupling caps).
* * * * * *
Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. Do not route any digital signals between the LXT9785/LXT9785E and the RJ-45 connectors at the edge of the board. edge of the board. Use this area for chassis ground, or leave it void.
* Do not extend any circuit power and ground plane past the center of the magnetics or to the 5.2.1 Power Supply Filtering
Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and degrade line performance. The best approach to this problem is to minimize ground noise as much as possible using good general techniques and by filtering the VCC plane. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems:
* Poorly-regulated or over-burdened power supplies. * Wide data busses (32-bits+) running at a high clock rate. * DC-to-DC converters.
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Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785/LXT9785E, helping with line performance. Second, if the VCC planes are laid out correctly, digital switching noise is kept away from external connectors, reducing EMI problems. The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT9785/LXT9785E. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one the LXT9785/LXT9785E, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. Beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10F) should be placed on each side of each bead. In addition, a high-frequency bypass cap (0.01 F) should be placed near each analog VCC pin.
5.2.2
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
* Follow the guidelines in the LXT9785 Design and Layout Guide (formerly Application Note
151) for locating the split between the digital and analog VCC planes. the RJ-45 connectors.
* Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and * Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the
ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.
5.2.2.1
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2 kV isolation to the Bob Smith termination.
5.2.3
MII Terminations
Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785/ LXT9785E. Special trace layout consideration should be used when using the SMII interface. Keep all traces orthogonal and as short as possible. Whenever possible, route the clock and sync traces evenly between the longest and shortest data routes. This minimizes round-trip, clock-to-data delays and allows a larger margin to the setup and hold requirements.
5.2.4
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
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* * * * *
Place the magnetics as close as possible to the LXT9785/LXT9785E. Keep transmit pair traces as short as possible; both traces should have the same length. Avoid vias and layer changes as much as possible. Keep the transmit and receive pairs apart to avoid cross-talk. Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. mA may be used to supply center tap current to all ports.
* Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400
5.2.4.1 Magnetic Requirements
The LXT9785/LXT9785E requires a 1:1 ratio for both the receive transformers and the transmit transformers. The transmit isolation voltage should be rated at 1.5 kV to protect the circuitry from static voltages across the connectors and cables. The LXT9785/LXT9785E is a current driven transceiver that requires an external voltage (center tap) to drive the transmit signal. In order to support the Auto-MDIX functionality of the LXT9785/LXT9785E, the magnetic must provide a center tap for both the transmit and receive magnetic winding, with both connected to VCCT. See the LXT9785/LXT9785E Design and Layout Guide (249509-001) for magnetic testing with the LXT9785/LXT9785E. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. Table 50 provides the magnetics requirements. Table 50. Intel(R) LXT9785/LXT9785E Magnetics Requirements
Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - 40 35 Return Loss -16 -10 Nom 1:1 1:1 0.6 - 2 - - - - Max - - 1.1 - - - - - - Units - - dB H kV dB dB dB dB .1 to 60 MHz 60 to 100 MHz 30 MHz 80 MHz Test Condition
5.2.5
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with the LXT9785/LXT9785E. See the 100BASE-FX Fiber Optic Transceivers-Connecting a PECL/ LVPECL Interface Application Note (document number 250781) for detailed information on fiber interface designs and recommendations for Intel PHYs. The following should occur in 3.3 V fiber transceiver applications as shown in Figure 36:
* The transmit pair should be AC-coupled with 2.5 V supplies and re-biased to 3.3 V LVPECL
levels
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* The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note)
* The receive pair should be DC-coupled with an emitter current path for the fiber transceiver * The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 36 shows a typical example of an LXT9785/LXT9785E-to-3.3 V fiber transceiver interface. The following occurs in 5 V fiber transceiver applications as shown in Figure 37:
* The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels * The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to-
fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note) and re-biased to 1.2 V
* The receive pair should be AC-coupled with an emitter current path for the fiber transceiver * The signal detect pin on a 5 V fiber transceiver interface should use the logic translator
circuitry as shown in Figure 38. Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 37 shows a typical example of an LXT9785/LXT9785E-to-5 V fiber transceiver interface, while Figure 38 shows the interface circuitry for the logic translator.
5.2.6
LED Circuit
Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected through a current-limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin drives Low. The open-drain LED pins are 5 V tolerant, allowing use of either a 3.3 V or 5 V rail (a 2.5 V rail is unlikely to work with standard forward voltage LEDs). A 5 V rail eases LED component selection by allowing more common, high-forward voltage LEDs to be used. Refer to Figure 33 for a circuit illustration.
Figure 33. LED Circuit
VLED R
LEDn_m Inside Outside IC IC
VCCIO < VLED < 5 V + 5%
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5.3
Typical Application Circuits
Figure 34 through Figure 37 on page 171 show typical application circuits for the LXT9785/ LXT9785E. Figure 38 on page 172 shows the interface circuitry for the logic translator.
Figure 34. Intel(R) LXT9785/LXT9785E Power and Ground Supply Connections
SGND
GNDR/GNDT
0.01F
VCCR/VCCT Analog Supply Plane
+
10F
LXT9785/9785E
Ferrite Bead
Digital Supply Plane VCCD GNDD
0.01 F 0.01 F
10 F
+2.5 V
VCCIO
+ 2.5 V or +3.3 V +2. 5 V or +3.3 V
VCCPECL
0.1 F
GNDPECL
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Figure 35. Intel(R) LXT9785/LXT9785E Typical Twisted-Pair Interface
TPFOP
1:1
RJ-45
1 2 3
1
TPFON TPFIP
1:1
50
50
4
50
5 6
LXT9785/9785E
2
50
50 50
7 8
TPFIN
.01 F
* = 0.001 F / 2.0 kV * = 0.001 F / 2.0 kV
VCCT
0.1F .01F
GNDA
1. The 100 transmit load termination resistor typically required is integrated in the LXT9785/ LXT9785E. 2. The 100 receive load termination resistor typically required is integrated in the LXT9785/
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Figure 36. Recommended Intel(R) LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry
+3.3V +2.5V +2.5V
27
0.01F - 0.1F 50
0.01F - 0.1F
1.4k
1.3k
50 TPFONn TPFOPn
0.01 F TD TD + 0.01 F 2k 2k
3.3V Fiber Txcvr To Fiber Network
LXT9785(E)
+3.3V
130 SDn 82 SD
1
TPFINn TPFIPn 130 SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers' recommendations for termination circuitry.
3.3V
RD RD + 130
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Figure 37. Recommended Intel(R) LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry
+2.5V +2.5V +5V
27
0.01F - 0.1F 50 1.15k 0.01F 1.1k
0.01F - 0.1F
50 TPFONn
TD 0.01F TD + 3.1k 3.1k
TPFOPn
LXT9785(E)
5V Fiber Txcvr To Fiber Network
2
SDn
ON Semiconductor* MC100LVEL92 PECL-to-LVPECL Logic Translator
SD
+2.5V
0.01F - 0.1F
127
127
1
0.01F TPFINn TPFIPn 118 SD_2P5V GNDPECL VCCPECL
3.3V
RD RD +
0.01F 118 270 270
1. Refer to the transceiver manufacturers' recommendations for termination circuitry. 2. See Figure 38 on page 172 for recommended logic translator interface circuitry.
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Figure 38. ON Semiconductor Triple PECL-to-LVPECL Translator
5V
0.01 F 0.01 F
5V
ON Semiconductor* PECL Input Signal (5V Fiber Txcvr)
3.3V 82 130
LVPECL Output Signal (LXT9785)
1 2
Vcc D0 __ D0 VBB PECL D1 __ D1 VBB PECL D2 __ D2 GND MC100LVEL92
Vcc Q0 __ Q0 LVCC Q1 __ Q1 LVCC Q2 __ Q2 Vcc
20 19 18 17 16 15 14 13 12 11
130
3 4 5 6 7 8 9 10
82 3.3V
3.3V 130
0.01 F
82
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6.0
Note:
Test Specifications
Table 51 through Table 81 and Figure 39 through Figure 62 represent the target specifications of the LXT9785/LXT9785E. These specifications are not guaranteed and are subject to change without notice. Minimum and maximum values listed in Table 53 through Table 81 apply over the recommended operating conditions specified in Table 52.
Table 51. Intel(R) LXT9785/LXT9785E Absolute Maximum Ratings
Parameter Sym Min Max Units
Supply voltage Storage temperature
VCCIO, VCCPECL VCCA, VCCD TST
-0.3 -0.3 -65
4.0 3.0 +150
V V C
Caution:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 52. Intel(R) LXT9785/LXT9785E Operating Conditions (Sheet 1 of 2)
Parameter Sym Min Typ1 (2.5 VCCIO) Typ1 (3.3 VCCIO) Max Units
Commercial Operating Temperature Extended Operating Temperature
Ambient Case Ambient Case Analog & Digital
TOPA TOPC TOPA TOPC Vcca, Vccd Vccio VCCPECL ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO
0 0 -40 -40 2.38 2.38 3.14 2.38 - - - - - - - - - -
- -
- -
70 108 85 123
C C C C V V V V mA mA mA mA mA mA mA mA mA mA
2.5 2.5 N/A 2.5 780 60 380 90 710 30 20 2 500 2
2.5 3.3 3.3 N/A
2.63 3.46 3.46 2.63 810
Supply voltage2
I/O I/O (SD_2P5V = 0) I/O (SD_2P5V = 1) 100BASE-TX
130
160 410
100BASE-FX Operating Current - RMII3
170
200 765
10BASE-T Power-Down Mode Hardware Auto-Negotiation
70
90 20
3
4 540
4
4
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 3. Values are aggregated for all eight ports.
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Table 52. Intel(R) LXT9785/LXT9785E Operating Conditions (Sheet 2 of 2)
Parameter Sym Min Typ1 (2.5 VCCIO) Typ1 (3.3 VCCIO) Max Units
100BASE-TX
ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO ICC ICCIO
- - - - - - - - - - - - - - - - - - - - 50 3 90 90 90 20 3 60 90 70
800 130 380 170 740 110 50 5 520 30 800 170 380 170 740 150 30 5 530 70
830 160 410 200 770 130 50 5 570 30 835 200 410 200 780 180 40 5 570 80
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
100BASE-FX Operating Current - SMII3
10BASE-T Power-Down Mode Hardware Auto-Negotiation
100BASE-TX
100BASE-FX Operating Current SS-SMII3
10BASE-T Power-Down Mode Hardware Auto-Negotiation
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 3. Values are aggregated for all eight ports.
Table 53. Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 2.5 V +/5%)
Parameter Sym Min Typ1 Max Units Test Conditions
Input Low voltage Input High voltage Input current Output Low voltage Output Low voltage (LEDm_n pins) Output High voltage
VIL VIH II VOL VOL-LED VOH
- 1.75 -100 - - 2.07
- - - - - -
0.75 - 100 0.2 0.5 -
V V A V V V
- - 0.0 < VI < VCC IOL = 4 mA IOL = 10 mA IOH = -4 mA
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Table 54. Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/5%)
Parameter Sym Min Typ1 Max Units Test Conditions
Input Low voltage Input High voltage Input current Output Low voltage Output Low voltage (LEDm_n pins) Output High voltage
VIL VIH II VOL VOL-LED VOH
- 2.0 -100 - - 2.4
- - - - - -
0.8 - 100 0.2 0.5 -
V V A V V V
- - 0.0 < VI < VCC IOL = 4 mA IOL = 10 mA IOH = -4 mA
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 55. Intel(R) LXT9785/LXT9785E Digital I/O DC Electrical Characteristics - SD Pins
Parameter Sym Min Typ1 Max Units Test Conditions
2.5 V Operation
Input Low voltage Input High voltage
VIL VIH
0.69 1.34
0.8 1.6
1.03 1.62
V V
VCCPECL = 2.5 V VCCPECL = 2.5 V
3.3 V Operation
Input Low voltage Input High voltage
VIL VIH
1.49 2.14
1.6 2.4
1.83 2.42
V V
VCCPECL = 3.3 V VCCPECL = 3.3 V
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. For 2.5 V operation, SD_2P5V = VCCPECL and VCCPECL=2.5 V. 3. For 3.3 V operation, SD_2P5V = GNDPECL or Floating and VCCPECL=3.3 V.
Table 56. Intel(R) LXT9785/LXT9785E Required Clock Characteristics
Parameter Sym Min Typ2 Max Units Test Conditions
SMII Input frequency RMII Input frequency Input clock frequency tolerance1 Input clock duty cycle
1
f f f Tdc Tdc Tdc
- - - 35 40 45
125 50 - 50 50 50
- - 50 65 60 55
MHz MHz ppm % % %
- - - RMII selection SMII/SS-SMII selection SS-SMII only
Input clock duty cycle - REFCLK, TxCLK1 Output RxCLK duty cycle
1. Parameter is guaranteed by design; not subject to production testing. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Table 57. Intel(R) LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics
Parameter Sym Min Typ1 Max Units Test Conditions
Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Jitter magnitude (measured differentially)
VP Vss trf trfs - VO ttx-jit
0.95 98 3 - - - -
- - - - - - -
1.05 102 5 0.5 +/- 0.5 5 1.4
V % ns ns ns % ns
Note 2 Note 2 Note 2 Note 2 Offset from 16 ns pulse width at 50% of pulse peak - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 (+/-1%) resistor.
Table 58. Intel(R) LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics
Parameter Sym Min Typ1 Transmitter Max Units Test Conditions
Peak-to-peak differential output voltage Signal rise/fall time Jitter magnitude (measured differentially)
VDIFFP-P trf ttx-jit
0.6 - -
1.44 - -
Receiver
- 1.8 1.4
V ns ns
- Note 2 -
Peak differential input voltage Common mode input range Input Low Voltage (SD pins) Input High Voltage (SD Pins)
VIP VCMIR VIL VIH
0.55 - VCC -1.84 VCC -1.04
- -
- VCC - 0.5 VCC -1.63 VCC -0.88
V V V V
- - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. 20 - 80 percent into 100 equivalent load of a typical fiber transceiver.
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Table 59. Intel(R) LXT9785/LXT9785E 10BASE-T Transceiver Characteristics
Parameter Sym Min Typ1 Max Units Test Conditions
Transmitter
Peak differential output voltage Link transmit period Jitter magnitude added by the MAU and PLS sections 3, 4
VOP - ttx-jit
2.2 8 -
2.5 - -
2.8 24 11
V ms ns
Note 2 - -
Receiver
Receive input impedance3 Link min receive timer Link max receive timer Differential squelch threshold
ZIN TLRmin TLRmax VDS
- 2 50 -
100 - - 475
- 7 150 -
W ms ms mV Peak
Between TPFIP and TPFIN - - 5 MHz square wave input
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. 4. After line model specified by IEEE 802.3 for 10BASE-T MAU.
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Figure 39. Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing
REFCLK t5 SYNC t1 RxData t3 TPFI t4 t2 t6
Table 60. Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS deasserted SYNC setup to REFCLK rising edge SYNC hold from REFCLK rising edge
t1 t2 t3 t4 t5 t6
1.5 - - - 1.5 1.0
- 1.0 21 25 - -
5 - 29 30 - -
ns ns BT2 BT2 ns ns
Minimum CL = 5 pF Maximum CL = 20 pF - Synchronous sampling of SMII Synchronous sampling of SMII - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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Figure 40. Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing
REFCLK t1 SYNC t2 t1
t2
TxData t3 TPFO
Table 61. Intel(R) LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold from REFCLK rising edge and TxData hold from REFCLK rising edge TxEN sampled to start of /J/
t1 t2 t3
1.5 1.0 -
- - 11
- - 18
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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Figure 41. Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing
REFCLK t5 SYNC t1 RxData t3 TPFI t4 t2 t6
Table 62. Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS deasserted SYNC setup to REFCLK rising edge SYNC hold from REFCLK rising edge
t1 t2 t3 t4 t5 t6
1.5 - - - 1.5 1.0
- 1 18 23 - -
5 - 26 27 - -
ns ns BT2 BT2 ns ns
Minimum CL = 5 pF Maximum CL = 20 pF - Synchronous sampling of SMII Synchronous sampling of SMII - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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Figure 42. Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing
REFCLK t1 SYNC t2 t1
t2
TxData t3 TPFO
Table 63. Intel(R) LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold from REFCLK rising edge and TxData hold from REFCLK rising edge TxEN sampled to start of /J/
t1 t2 t3
1.5 1.0 -
- - 10
- - 17
ns ns BT2
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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Figure 43. Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Receive Timing
REFCLK t5 SYNC t1 RxData t3 TPFI t4 t2 t6
Table 64. Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData output delay from REFCLK rising edge RxData Rise/Fall Time Receive Start-of-Frame to CRS asserted Receive Start-of-Idle to CRS de-asserted SYNC setup to REFCLK rising edge SYNC hold from REFCLK rising edge
t1 t2 t3 t4 t5 t6
1.5 - - - 1.5 1.0
- 1 17 17 - -
5 - 21 18 - -
ns ns BT3 BT3 ns ns
Minimum CL = 5 pF Maximum CL = 20 pF - Synchronous sampling of SMII2 Synchronous sampling of SMII2 - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Assumes each SMII segment is sampled for CRS. 3. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 44. Intel(R) LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing
REFCLK t1 SYNC t2 t1
t2
TxData t3 TPFO
Table 65. Intel(R) LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
SYNC setup to REFCLK rising edge and TxData setup to REFCLK rising edge SYNC hold to REFCLK rising edge and TxData hold from REFCLK rising edge TxEN sampled to start-of-frame
t1 t2 t3
1.5 1.0 -
- - 10
- - 14
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 45. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing
REFCLK t1 RxCLK t2 RxSYNC t3 t3
t3
RxData t4 TPFI t5
Table 66. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de-asserted
t1 t2 t3 t4 t5
- 1.5 - - -
1.5 - 1.0 21 25
- 5 - 27 30
ns ns ns BT2 BT2
- Minimum CL = 5pF Maximum CL = 40pF - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 46. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
TxCLK t1 TxSYNC t2 t1
t2
TxData t3 TPFO
Table 67. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing
Parameter Sym Min Typ1 Max Units Test Conditions
TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold from TxCLK rising edge and TxData hold to TxCLK rising edge TxEN sampled to start of /J/
t1 t2 t3
1.5 1.0 -
- - 11
- - 18
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 47. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing
REFCLK t1 RxCLK t2 RxSYNC t3 t3
t3
RxData t4 TPFI t5
Table 68. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time Receive start of /J/ to CRS asserted Receive start of /T/ to CRS de-asserted
t1 t2 t3 t4 t5
- 1.5 - - -
1.5 - 1 18 21 5 - 23 26
ns ns ns BT2 BT2
- Minimum CL = 5pF Maximum CL = 40pF - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 48. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing
TxCLK t1 TxSYNC t2 t1
t2
TxData t3 TPFO
Table 69. Intel(R) LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold from TxCLK rising edge and TxData hold to TxCLK rising edge TxData to TPFO Latency
t1 t2 t3
1.5 1.0 -
- - 11
- - 13
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 49. Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing
REFCLK t1 RxCLK t2 RxSYNC
t3
RxData t4 TPFI t5
Table 70. Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
REFCLK rising edge to RxCLK rising edge RxData/RxSYNC output delay from RxCLK rising edge RxData/RxSYNC Rise/Fall time Receive Start-of-Frame to CRS asserted Receive Start-of-Idle to CRS de-asserted
t1 t2 t3 t4 t5
- 1.5 - - -
1.5 - 1 10 18
- 5 - 11 21
ns ns ns BT3 BT3
- Minimum CL = 5pF Maximum CL = 40pF - Synchronous sampling of SMII2 Synchronous sampling of SMII2
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Assumes each SMII segment is sampled for CRS. 3. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 50. Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing
TxCLK t1 TxSYNC t2 t1
t2
TxData t3 TPFO
Table 71. Intel(R) LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
TxSYNC setup to TxCLK rising edge and TxData setup to TxCLK rising edge TxSYNC hold to TxCLK rising edge and TxData hold from TxCLK rising edge TxData to TPFO Latency
t1 t2 t3
1.5 1.0 -
- - 10
- - 14
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 51. Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing
REFCLK t1 RxData[1:0] t2
TPFI t3 CRS_DV t4
Table 72. Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData<1:0>, CRS_DV, RXER setup to REFCLK rising edge3 RxData<1:0>, CRS_DV, RXER hold from REFCLK rising edge3 Receive start of /J/ to CRS_DV asserted Receive start of /T/ to CRS_DV de-asserted
t1 t2 t3 t4
4 2 - -
- - 16 20
14 14 21 27
ns ns BT2 BT
2
- - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). 3. Values and conditions from RMII Specification, Rev. 1.2. NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 52. Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing
REFCLK t1 TxData(1:0) t2
TPFO t1 t3 t2
TxEN
Table 73. Intel(R) LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TxEN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency)
t1 t2 t3
4 2 -
- - 12
- - 17
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 53. Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing
REFCLK t1 RxData[1:0] t2
TPFI t3 CRS_DV t4
Table 74. Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData<1:0>, CRS_DV, RXER setup to REFCLK rising edge3 RxData<1:0>, CRS_DV, RXER hold from REFCLK rising edge3 Receive start of /J/ to CRS_DV asserted Receive start of /T/ to CRS_DV de-asserted
t1 t2 t3 t4
4 2 - -
- - 14 18
14 14 18 25
ns ns BT2 BT
2
- - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). 3. Values and conditions from RMII Specification, Rev. 1.2. NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 54. Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing
REFCLK t1 TxData(1:0) t2
TPFO t1 t3 t2
TxEN
Table 75. Intel(R) LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TX-EN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency)
t1 t2 t3
4 2 -
- - 10
- - 12
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 55. Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Receive Timing
REFCLK t1 RxData[1:0] t2
TPFI t3 CRS_DV t4
Table 76. Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
RxData<1:0>, CRS_DV setup to REFCLK rising edge3 RxData<1:0>, CRS_DV hold from REFCLK rising edge3 TPFI in to CRS_DV asserted TPFI quiet to CRS_DV de-asserted
t1 t2 t3 t4
4 2 1.5 12
- - 3 15
14 14 4 16
ns ns BT2 BT
2
- - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). 3. Values and conditions from RMII Specification, Rev. 1.2. NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 56. Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing
REFCLK t1 TxData(1:0) t2
TPFO t1 t3 t2
TxEN
Table 77. Intel(R) LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
TxData<1:0>/TxEN setup to REFCLK rising edge TxData<1:0>/TxEN hold from REFCLK rising edge TxEN sampled to TPFO out (Tx latency)
t1 t2 t3
4 2 -
- - 8.5
- - 14
ns ns BT2
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. "BT" signifies bit times at the line rate (that is, BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-TX or 100BASE-FX). NOTE: The table latency values are derived with the hardware configuration pins FIFOSEL[1:0] set at a default configuration of 00 (32 bits of initial fill).
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 57. Intel(R) LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse Data Pulse Clock Pulse
TPFOP
t1 t2 t1 t3
Figure 58. Intel(R) LXT9785/LXT9785E Fast Link Pulse Timing
FLP Burst FLP Burst
TPFOP
t4 t5
Table 78. Intel(R) LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst
t1 t2 t3 t4 t5 -
- 55.5 111 - 8 17
100 - - 2 - -
- 69.5 139 - 24 33
ns s s ms ms ea
- - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 59. Intel(R) LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC)
MDC
t1 t2
MDIO
Figure 60. Intel(R) LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY)
MDC t3
MDIO
Table 79. Intel(R) LXT9785/LXT9785E MDIO Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY
t1 t2 t3
10 10 0
- - -
- - 40
ns ns ns
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 61. Intel(R) LXT9785/LXT9785E Power-Up Timing
v1
VCC MDIO,etc tPDR
Table 80. Intel(R) LXT9785/LXT9785E Power-Up Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
Voltage Threshold Power-up recovery time Software power-down2
v1 tPDR tSPDR
2.1 100 20
- - -
- - -
V ms ms
- - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. The minimum time required between bringing up consecutive ports powered down by Register bit 0.11, or a software or hardware reset.
Figure 62. Intel(R) LXT9785/LXT9785E Reset Recovery Timing
tPW
RESET
tRcdly
MDIO,etc
Table 81. Intel(R) LXT9785/LXT9785E Reset Recovery Timing Parameters
Parameter Sym Min Typ1 Max Units Test Conditions
Reset pulse width Reset recovery delay
tPW tRcdly
10 0.4
- -
- -
ns ms
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
7.0
Register Definitions
The LXT9785/LXT9785E register set includes multiple 16-bit registers, 18 registers per port. Table 82 presents a complete register listing. Table 83, "Control Register (Address 0)" on page 200 through Table 100, "Cable Diagnostics Register (Address 29, Hex 1D)" on page 217 define individual registers and Table 101, "Intel(R) LXT9785/LXT9785E Register Bit Map" on page 219 provides a consolidated memory map of all registers. Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation" sections of the IEEE 802.3 standard. Additional registers (16 through 21, 25, 27, and 29) are defined in accordance with the IEEE 802.3 standard for adding unique chip functions. The BGA15 package on some registers has different default values. Some LXT9785 features are not available on the BGA15 package. These differences are called out in the register description and in the table notes in individual register tables.
Table 82. Intel(R) LXT9785/LXT9785E Register Set (Sheet 1 of 2)
Address Register Name Bit Assignments
0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21 22-24 25 26
"Control Register (Address 0)" "Status Register (Address 1)" "PHY Identification Register 1 (Address 2)" "PHY Identification Register 2 (Address 3)" "Auto-Negotiation Advertisement Register (Address 4)" "Auto-Negotiation Link Partner Base Page Ability Register (Address 5)" "Auto-Negotiation Expansion Register (Address 6)" "Auto-Negotiation Next Page Transmit Register (Address 7)" "Auto-Negotiation Link Partner Next Page Receive Register (Address 8)" 1000BASE-T/100BASE-T2 Control 1000BASE-T/100BASE-T2 Status Extended Status "Port Configuration Register (Address 16, Hex 10)" "Quick Status Register (Address 17, Hex 11)" "Interrupt Enable Register (Address 18, Hex 12)" "Interrupt Status Register (Address 19, Hex 13)" "LED Configuration Register (Address 20, Hex 14)" "Receive Error Count Register (Address 21, Hex 15)" Reserved "RMII Out-of-Band Signaling Register (Address 25, Hex 19)" Reserved
Refer to Table 83 on page 200 Refer to Table 84 on page 201 Refer to Table 85 on page 203 Refer to Table 86 on page 203 Refer to Table 87 on page 204 Refer to Table 88 on page 205 Refer to Table 89 on page 206 Refer to Table 90 on page 206 Refer to Table 91 on page 207 Not Implemented Not Implemented Not Implemented Refer to Table 92 on page 207 Refer to Table 93 on page 209 Refer to Table 94 on page 211 Refer to Table 95 on page 212 Refer to Table 96 on page 213 Refer to Table 97 on page 214 N/A Refer to Table 98 on page 215 N/A
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 82. Intel(R) LXT9785/LXT9785E Register Set (Sheet 2 of 2)
Address Register Name Bit Assignments
27 28 29 30 - 31
"Trim Enable Register (Address 27, Hex 1B)" Reserved "Cable Diagnostics Register (Address 29, Hex 1D)" Reserved
Refer to Table 99 on page 216 N/A Refer to Table 100 on page 217 N/A
Table 83. Control Register (Address 0) (Sheet 1 of 2)
Bit Name Description Type1 Default
15
RESET
0 = Normal operation 1 = PHY reset 0 = Disable loopback mode 1 = Enable loopback mode
R/W SC
02
14
Loopback
Not recommended to enable auto-negotiation while in internal loopback operation.
R/W
0
0.6 13 Speed Selection 1 1 0 0
0.13 1 = Reserved 0 = 1000 Mbps (not allowed) 1 = 100 Mbps 0 = 10 Mbps R/W LSHR3,4
12
Auto-Negotiation Enable Power-Down
0 = Disable auto-negotiation process 1 = Enable auto-negotiation process 0 = Normal operation 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from RMII/SMII/SSSMII interfaces 0 = Normal operation 1 = Restart auto-negotiation process 0 = Half-duplex 1 = Full-duplex
R/W
LSHR3,4 LSHR3,5
11
R/W
10
Isolate Restart Auto-Negotiation Duplex Mode
R/W R/W SC R/W
0
9 8
0 LSHR3,4
1. R/W = Read/Write, SC = Self Clearing when operation complete. 2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the LSHR information is not re-read from the pins. This information reverts back to the information that was read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The reset bit should be polled to see when the part has completed reset. 3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42, "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129. 5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 83. Control Register (Address 0) (Sheet 2 of 2)
Bit Name Description Type1 Default
This bit is ignored by the LXT9785/LXT9785E 7 Collision Test 0 = Disable COL signal test 1 = Enable COL signal test 0.6 6 Speed Selection 1000 Mbps 1 1 0 0 0.13 1 = Reserved 0 = 1000 Mbps (not allowed) 1 = 100 Mbps 0 = 10 Mbps R/W 0 R/W 0
5:0
Reserved
Write as 0, ignore on Read
R/W
000000
1. R/W = Read/Write, SC = Self Clearing when operation complete. 2. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the LSHR information is not re-read from the pins. This information reverts back to the information that was read in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms after de-assertion of the reset. During a software reset (0.15) the registers are available for reading. The reset bit should be polled to see when the part has completed reset. 3. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 4. Default value of Register bits 0.12, 0.13, and 0.8 are determined by the CFG pins as described in Table 42, "Intel(R) LXT9785/9785E Global Hardware Configuration Settings" on page 129. 5. Default value of Register bit 0.11 is determined by the LINKHOLD configuration pin.
Table 84. Status Register (Address 1)
Bit Name Description Type1,2 Default
15 14 13
100BASE-T4 100BASE-X Full-Duplex 100BASE-X Half-Duplex 10 Mbps Full-Duplex
0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to operate at 10 Mbps in full-duplex mode 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASE-T2 1 = PHY able to perform half-duplex 100BASE-T2 0 = No extended status information in Register 15 1 = Extended status information in Register 15 Write as 0, ignore on Read 0 = PHY will not accept management frames with preamble suppressed 1 = PHY accepts management frames with preamble suppressed
R R R
0 1 1
12
R
1
11 10 9 8 7 6
10 Mbps Half-Duplex 100BASE-T2 Full-Duplex 100BASE-T2 Half-Duplex Extended Status Reserved MF Preamble Suppression
R R R R R R
1 0 0 0 0 0
1. R = Read Only 2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
Datasheet
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Table 84. Status Register (Address 1)
Bit Name Description Type1,2 Default
5 4 3 2 1 0
Auto-Negotiation complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability
0 = Auto-negotiation not complete 1 = Auto-negotiation complete 0 = No remote fault condition detected 1 = Remote fault condition detected 0 = PHY is not able to perform auto-negotiation 1 = PHY is able to perform auto-negotiation 0 = Link is down 1 = Link is up 0 = Jabber condition not detected 1 = Jabber condition detected 0 = Basic register capabilities 1 = Extended register capabilities
R R/LL R R/LL R/LH R
0 0 1 0 0 1
1. R = Read Only 2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.
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Table 85. PHY Identification Register 1 (Address 2)
Bit Name Description Type1 Default
15:0
PHY ID Number
The PHY identifier composed of bits 3 through 18 of the OUI
R
0013 hex
1. R = Read Only
Table 86. PHY Identification Register 2 (Address 3)
Bit Name Description Type1 Default
15:10 9:4 3:1
PHY ID Number Manufacturer's Model Number Manufacturer's Revision Number Model Variant
The PHY identifier composed of bits 19 through 24 of the OUI 6 bits containing manufacturer's part number 3 bits containing manufacturer's revision number 0 = LXT9785 1 = LXT9785/LXT9785E
R R R
011110 001111 XXX2
0
R
X2
1. R = Read Only 2. Refer to the Identification Information section in the Intel(R) LXT9785/LXT9785E Specification Update.
Figure 63. PHY Identifier Bit Mapping
a b c r s x
Organizationally Unique Identifier
1 2 3 0 I/G 15 0 1 3 0 15 10 9 4 3 0 18 19 24
PHY ID Register #1 (Address 2)
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1
PHY ID Register #2 (Address 3)
1 1 0 X X X X X X X X X X
0
0
0
2
B
7 5 0 3 1 0
00
20
7B
The Intel OUI is 00207B hex.
Manufacturer's Model Number
Revision Number Model Variant
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 87. Auto-Negotiation Advertisement Register (Address 4)
Bit Name Description Type1 Default
0 = Port has no ability to send manual next pages 1 = Port has ability to send manual next pages 15 Next Page
Note: This bit should only be set to manually control the autonegotiation process. It is not needed and should be cleared for DTE Discovery.
R/W
0
14 136 12 11
Reserved Remote Fault Reserved Asymmetric Pause
Write as 0, ignore on Read 0 = No remote fault 1 = Remote fault Write as 0, ignore on Read Pause operation defined in Clause 40 and 27 0 = Port is not Pause capable 1 = Port can only send Pause 0 = Pause operation disabled 1 = Port can send and receive Pause
NOTE: Default for the BGA15 package is 0.
R R/W R/W R/W
0 0 0 0
10
Pause5
R/W
LSHR2,3
0 = 100BASE-T4 capability is not available 1 = 100BASE-T4 capability is available 9 100BASE-T4 (The LXT9785/LXT9785E does not support 100BASE-T4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 0 = Port is not 100BASE-TX full-duplex capable. 1 = Port is 100BASE-TX full-duplex capable 0 = Port is not 100BASE-TX half-duplex capable 1 = Port is 100BASE-TX half-duplex capable 0 = Port is not 10BASE-T full-duplex capable 1 = Port is 10BASE-T full-duplex capable 0 = Port is not 10BASE-T half-duplex capable 1 = Port is 10BASE-T half-duplex capable <00001> = IEEE 802.3 <00010> = IEEE 802.9 ISLAN-16T <00000> = Reserved for future auto-negotiation development <11111> = Reserved for future auto-negotiation development Unspecified or reserved combinations should not be transmitted R/W 0
8 7 6 5
100BASE-TX Full-Duplex 100BASE-TX Half-Duplex 10BASE-T Full-Duplex 10BASE-T Half-Duplex Selector Field, S<4:0>
R/W R/W R/W R/W
LSHR2,4 LSHR2,4 LSHR2,4 LSHR2,4
4:0
R/W
00001
1. R/W = Read/Write, R = Read Only 2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 3. The default setting of Register bit 4.10 is determined by the PAUSE pin. The BGA15 package does not have a Pause hardware configuration pin and has a default of 0. 4. Default settings for bits 4.5:8 are determined by CFG pins as described in Table 42, "Intel(R) LXT9785/ 9785E Global Hardware Configuration Settings" on page 129. 5. Pause operation is only valid for full-duplex modes. 6. If Register bit 4.13 is set to advertise a fault, Register bit 1.4 will be set. NOTE: Restart the auto-negotiation process whenever Register 4 is written/modified.
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Table 88. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Bit Name Description Type1 Default2
15
Next Page
0 = Link partner has no ability to send multiple pages 1 = Link partner has ability to send multiple pages 0 = Link partner has not received Link Code Word from the the LXT9785/LXT9785E 1 = Link partner has received Link Code Word from the LXT9785/LXT9785E. 0 = No remote fault 1 = Remote fault Write as 0, ignore on Read Pause operation defined in Clause 40 and 27 0 = Link partner is not Pause capable 1 = Link partner can only send Pause 0 = Link partner is not Pause capable 1 = Link partner can send and receive Pause 0 = Link partner is not 100BASE-T4 capable 1 = Link partner is 100BASE-T4 capable 0 = Link partner is not 100BASE-TX full-duplex capable 1 = Link partner is 100BASE-TX full-duplex capable 0 = Link partner is not 100BASE-TX capable 1 = Link partner is 100BASE-TX capable 0 = Link partner is not 10BASE-T full-duplex capable 1 = Link partner is 10BASE-T full-duplex capable 0 = Link partner is not 10BASE-T capable 1 = Link partner is 10BASE-T capable <00001> = IEEE 802.3 <00010> = IEEE 802.9 ISLAN-16T <00000> = Reserved for future auto-negotiation development <11111> = Reserved for future auto-negotiation development Unspecified or reserved combinations shall not be transmitted
R
0
14
Acknowledge
R
0
13 12 11
Remote Fault Reserved Asymmetric Pause Pause 100BASE-T4 100BASE-TX Full-Duplex 100BASE-TX 10BASE-T Full-Duplex 10BASE-T
R R R
0 0 0
10 9 8 7 6 5
R R R R R R
0 0 0 0 0 0
4:0
Selector Field S<4:0>
R
00000
1. R = Read Only 2. Default value at the start of auto-negotiation code word transmission.
Datasheet
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Table 89. Auto-Negotiation Expansion Register (Address 6)
Bit Name Description Type1 Default
15:5 4 3 2
Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able
Write as 0, ignore on Read 0 = Parallel detection fault has not occurred 1 = Parallel detection fault has occurred 0 = Link partner is not next page able 1 = Link partner is next page able 0 = Local device is not next page able 1 = Local device is next page able Indicates that a new page has been received and the received code word has been loaded into Register 5 or Register 8 as specified in clause 28 of 802.3.
R R/ LH R R
0x000 0 0 1
1
Page Received
0 = Three identical and consecutive link code words have not been received from link partner 1 = Three identical and consecutive link code words have been received from link partner 0 = Link partner is not auto-negotiation able 1 = Link partner is auto-negotiation able
R/ LH
0
0
Link Partner A/N Able
R
0
1. R = Read Only, LH = Latching High - cleared when read
Table 90. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit Name Description Type1 Default
15 14 13 12
Next Page (NP) Reserved Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field
0 = Last page 1 = Additional next pages follow Write as 0, ignore on Read. 0 = Unformatted page 1 = Message page 0 = Cannot comply with message 1 = Complies with message 0 = Previous value of the transmitted link code word equalled logic one 1 = Previous value of the transmitted link code word equalled logic zero MP = 0: Code interpreted as "unformatted page" MP = 1: Code interpreted as "message page"
R/W R R/W R/W
0 0 1 0
11
R
0
10:0
R/W
0000000 0001
1. R/W = Read Write, R = Read Only
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Table 91. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit Name Description Type1 Default2
15
Next Page (NP) Acknowledge (ACK) Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/ Unformatted Code Field
0 = Link partner has no additional next pages to send 1 = Link partner has additional next pages to send 0 = Link partner has not received Link Code Word from the LXT9785/LXT9785E 1 = Link partner has received Link Code Word from the LXT9785/LXT9785E 0 = Page sent by the link partner is an unformatted page 1 = Page sent by the link partner is a message page 0 = Link partner cannot comply with the message 1 = Link partner complies with the message 0 = Previous value of the transmitted Link Code Word equalled logic one 1 = Previous value of the transmitted Link Code Word equalled logic zero MP = 1: Code interpreted as message page MP = 0: Code interpreted as unformatted page
R
0
14
R
0
13 12
R R
0 0
11
R
0
10:0
R
0x000
1. R = Read Only 2. Default value at the start of auto-negotiation code word transmission.
Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 1 of 2)
Bit Name Description Type 1 Default
15
Reserved
Write as 0, ignore on Read 0 = Normal operation 1 = Force link pass (sets appropriate registers and LEDs to pass)
R/W
0
14
Link Disable
Note: Setting this bit in 100 Mbps mode by-passes the descrambler lock requirement to establish link and forces the link to the link-good state. Setting this bit produces unreliable results if the descrambler is not locked,
R/W
0
13 12 11 10
Transmit Disable Bypass Scramble (100BASE-TX) Reserved Jabber (10BASE-T)
0 = Normal operation 1 = Disable twisted-pair transmitter 0 = Normal operation 1 = Bypass scrambler and descrambler Write as 0, ignore on Read 0 = Normal operation 1 = Jabber function is enabled; however, jabber status reporting to Register bit 1.1 is disabled
R/W R/W R/W R/W
0 0 0 0
1. R/W = Read/Write 2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 3. The default value of Register bit 16.0 is determined by the G_FX/TP pin. If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin. 4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not have a PREASEL hardware configuration pin and has a default of 0. 5. The BGA15 package does not support fiber. Default for the BGA15 package is 0. 6. NA means the bits do not have a default value and may initially contain any value.
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Table 92. Port Configuration Register (Address 16, Hex 10) (Sheet 2 of 2)
Bit Name Description Type 1 Default
9
Reserved TP Loopback (10BASE-T) Reserved Reserved
Write as 0, ignore on Read. 0 = Normal operation 1 = Disable twisted-pair loopback during half-duplex operation
Note: Valid function in SMII and S-SMII modes only.
R/W
0
8
R/W
1
7 6
Write as 1, ignore on Read Write as 0, ignore on Read 10 Mbps 0 = No preamble (default) 1 = Preamble enabled NOTE: Default for BGA15 package is 0. No effect
R/W R/W
1 0 LSHR2,4
5
Preamble Enable 100 Mbps
R/W N/A R/W R/W 0 0
4 3
Reserved Reserved Far End Fault Transmission Enable Invalid for BGA15
Write as 0, ignore on Read Write as 0, ignore on Read 0 = Disable Far End Fault transmission 1 = Enable Far End Fault transmission Write as '0', ignore on Read (BGA15). Write as 0, ignore on Read. 0 = Select twisted-pair mode for this port 1 = Select fiber mode for this port Write as '0', ignore on Read (BGA15). NOTE: Default for BGA15 is 0.
2
R/W
1
1
Reserved Fiber Select5
R/W
0
0
Reserved for BGA15
R/W
LSHR2,3
1. R/W = Read/Write 2. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 3. The default value of Register bit 16.0 is determined by the G_FX/TP pin. If G_FX/TP is tied Low, the default value of Register bit 16.0 = 0. If G_FX/TP is not tied Low, the default value of Register bit 16.0 = 1. The BGA15 package does not have a G_FX/TP hardware configuration pin. 4. The default value of Register bit 16.5 is determined by the PREASEL pin. The BGA15 package does not have a PREASEL hardware configuration pin and has a default of 0. 5. The BGA15 package does not support fiber. Default for the BGA15 package is 0. 6. NA means the bits do not have a default value and may initially contain any value.
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Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 1 of 2)
Bit Name Description Type 1 Default2
15
Reserved
Write as 0, ignore on Read 0 = The LXT9785/LXT9785E is operating in 10 Mbps mode 1 = The LXT9785/LXT9785E is operating in 100 Mbps mode
NOTE: The status is valid for TX and FX operation.
R
0
14
10/100 Mode
R
0
13 12
Transmit Status Receive Status
0 = The LXT9785/LXT9785E is not transmitting a packet 1 = The LXT9785/LXT9785E is transmitting a packet 0 = Packet has not been received since last read 1 = Packet has been received since last read 0 = A collision is not occurring 1 = A collision is occurring
R LH R LH
0 0
11
Collision Status
NOTE: This bit is set when jabber is detected, regardless of duplex.
R LH
0
10 9
Link Duplex Mode
0 = Link is down 1 = Link is up 0 = Half-duplex 1 = Full-duplex 0 = The LXT9785/LXT9785E is in manual mode 1 = The LXT9785/LXT9785E is in auto-negotiation mode This signal is based upon Register bit 0.12. 0 = Auto-negotiation process is not complete 1 = Auto-negotiation process is complete 0 = No FIFO error occurred 1 = FIFO error occurred (overflow or underflow) 0 = Polarity is not reversed 1 = Polarity is reversed
R R
0 0
8
Auto-Negotiation Auto-Negotiation Complete FIFO Error
R
Note 3
7 6
R R LH
0 0
5
Polarity
NOTE: During 100 Mbps operation, this bit is not valid and may vary. Auto MDIX activity may increase the variability.
R
0
1. R = Read Only, LH = Latching High - cleared when read. 2. The default values are updated on completion of reset and reflect the status or change in status at that time. Intel recommends that the register status be read on completion of reset. 3. The default value is determined by the default value of Register bit 0.12. 4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a Pause hardware configuration pin. The default for the BGA15 package is 0.
Datasheet
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Table 93. Quick Status Register (Address 17, Hex 11) (Sheet 2 of 2)
Bit Name Description Type 1 Default2
0 = The LXT9785/LXT9785E is not Pause capable 1 = The LXT9785/LXT9785E is pause capable 4 Pause
NOTE: This bit is not affected by Register bit 4.10. NOTE: The default for the BGA15 package is 0.
R
LSHR4,5
3
Error
0 = No error occurred 1 = Error Occurred (remote fault, RxERCntFUL, FIFO error, jabber, parallel detect fault)
NOTE: The register is cleared when the registers that generated the error condition are read.
R
0
2:0
Reserved
Write as 0, ignore on Read.
R
0
1. R = Read Only, LH = Latching High - cleared when read. 2. The default values are updated on completion of reset and reflect the status or change in status at that time. Intel recommends that the register status be read on completion of reset. 3. The default value is determined by the default value of Register bit 0.12. 4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 5. Default values are set by the hardware configuration PAUSE pin. The BGA15 package does not have a Pause hardware configuration pin. The default for the BGA15 package is 0.
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Table 94. Interrupt Enable Register (Address 18, Hex 12)
Bit Name Description Type 1 Default
00 = Reserved 15:14
2
RxFIFO Initial Fill
01 = Low, 16 bits 10 = Normal, 32 bits (default) 11 = Jumbo packets, 128 bits When Register bit 16.5 = 1, preamble is not suppressed.
R/W
LSHR4,5
SFD Frame Alignment3 13 (RxDV asserts with CRS when enabled)
10 Mbps
0 = Disabled 1 = Enabled When Register bit 16.5 = 0, SFD is always aligned, and preamble is suppressed. 0 = Disabled 1 = Enabled When enabled, all but one byte of preamble is suppressed.
R/W
0
100 Mbps
R/W
0
12:9 8
Reserved CNTRMSK
Write as 0, ignore on Read Mask for Counter Full 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Mask for Auto-Negotiate Complete 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Mask for Speed Interrupt 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Mask for Duplex Interrupt 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Mask for Link Status Interrupt 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Mask for Isolate Interrupt 0 = Do not allow event to cause interrupt 1 = Enable event to cause interrupt Write as 0, ignore on Read 0 = Disable interrupts on this port 1 = Enable interrupts on this port 0 = Normal operation 1 = Test force interrupt on MDINT
R/W R/W
0000 0
7
ANMSK
R/W
0
6
SPEEDMSK
R/W
0
5
DUPLEXMSK
R/W
0
4
LINKMSK
R/W
0
3 2 1 0
ISOLMSK Reserved INTEN TINT
R/W R/W R/W R/W
0 0 0 0
1. R/W = Read/Write 2. In 10 Mbps operation, Register bit 18.13 = 1 cannot be used when Register bits 18.15:14 = "11" and in RMII mode, Registers bits 18.15:14 = "11" or "10" cannot be used because the minimum Inter Gap Packet becomes less than specified in the *IEEE 802.3 specification. 3. SFD Frame Alignment is applicable to SMII and SS-SMII only. 4. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset 5. Default values are set by hardware configuration pins FIFOSEL1 and FIFOSEL0 (see Table 17, "Intel(R) LXT9785/LXT9785E Receive FIFO Depth Considerations" on page 50).
Datasheet
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 95. Interrupt Status Register (Address 19, Hex 13)
Bit Name Description Type 1 Default2
15:9
Reserved
Write as 0, ignore on Read
RxER Counter Full Status.
R
0
8
RxERCntFUL
0 = The internal counters have not reached maximum values 1 = One of the internal counters has reached its maximum value
Auto-Negotiation Status.
R/LH
0
7
ANDONE
0 = Auto-negotiation has not completed 1 = Auto-negotiation has completed
Speed Change Status.
R/LH
N/A
6
SPEEDCHG
0 = A speed change has not occurred since last reading this register 1 = A speed change has occurred since last reading this register
Duplex Change Status.
R/LH
0
5
DUPLEXCHG
0 = A duplex change has not occurred since last reading this register 1 = A duplex change has occurred since last reading this register
Link Status Change Status.
R/LH
0
4
LINKCHG
0 = A link change has not occurred since last reading this register 1 = A link change has occurred since last reading this register
MII Isolate Change Status.
R/LH
0
3
Isolate
0 = An Isolate change has not occurred since last reading this register 1 = An Isolate change has occurred since last reading this register 0 = Interrupt not pending 1 = Interrupt pending Reserved
R/LH
0
2 1:0
MDINT Reserved
R/LH R
0 0
1. R = Read Only, LH = Latching High - cleared when read 2. The default values are updated on completion of reset and reflect the status or change in status at that time. Intel recommends that the register status be read on completion of reset.
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Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 1 of 2)
Bit Name Description Type1 Default
0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous) 0110 = Display Isolate Status (Continuous) 0111= Display Receive or Transmit Activity (Stretched) LED1 15:12 Programming bits 1000= est mode- turn LED on (Continuous) 1001= Test mode- turn LED off (Continuous) 1010= Test mode- blink LED fast (Continuous) 1011= Test mode- blink LED slow (Continuous) 1100= Display Link and Receive Status combined2 (Stretched)3 1101= Display Link and Activity Status combined2 (Stretched)3 1110= Display Duplex and Collision Status combined4 (Stretched)3 1111 = Display Link and RxER Status combined2 (Blink) 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Display Isolate Status 0111= Display Receive or Transmit Activity LED2 11:8 Programming bits 1000= Test mode- turn LED on 1001= Test mode- turn LED off 1010= Test mode- blink LED fast 1011= Test mode- blink LED slow 1100= Display Link and Receive Status combined2 (Stretched)3 1101= Display Link and Activity Status combined2 (Default) (Stretched)3 1110= Display Duplex and Collision Status combined4 (Stretched)3 1111= Display Link and RxER Status combined 2 (Blink) 1. R/W = Read/Write 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. R/W 1101 R/W 0000
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Table 96. LED Configuration Register (Address 20, Hex 14) (Sheet 2 of 2)
Bit Name Description Type1 Default
LED3 Programming bits
0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Display Isolate Status 0111= Display Receive or Transmit Activity 1000= Test mode- turn LED on 1001= Test mode- turn LED off 1010= Test mode- blink LED fast 1011= Test mode- blink LED slow 1100= Display Link and Receive Status combined2 (Stretched)3 1101= Display Link and Activity Status combined2 (Stretched)3 1110= Display Duplex and Collision Status combined4 (Default) (Blink)3 1111 = Display Link and RxER Status combined 2 (Blink)
7:4
R/W
1110
Reserved for BGA15
Write as '1001', ignore on Read (BGA15) 00 = Stretch LED events to 30 ms
3:2
LEDFREQ
01 = Stretch LED events to 60 ms 10 = Stretch LED events to 100 ms 11 = Reserved 0 = Disable pulse stretching of all LEDs3 1 = Enable pulse stretching of all LEDs
R/W
00
1
PULSESTRETCH
R/W
NOTE: Receive activity LEDs are initially active based upon carrier sense.
1
0
Reserved
Write as 0, ignore on Read
R/W
0
1. R/W = Read/Write 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.
Table 97. Receive Error Count Register (Address 21, Hex 15)
Bit Name Description Type1 Default
15:0
Receive Error Count
A 16-bit counter value indicating the number of times a receive packet with errors occurred. Only one event gets counted per packet. When maximum count is reached, the 16-bit counter remains full until cleared.
R/ LH
0x0000
1. R = Read Only, LH = Latching High - cleared when read NOTE: Intel recommends reading this register once every time link is established to clear the register.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 98. RMII Out-of-Band Signaling Register (Address 25, Hex 19)
Bit Name Description BGA15 Type1 Default
15:0
Reserved for BGA15
Write as 0, ignore on Read.
PQFP and BGA23
R/W
0x0000
15:7
Reserved
Write as 0, ignore on Read These three bits select which status information is available on the RxData(1) bit of the RMII bus. 000 = Link 001 = Speed 010 = Duplex 011 = Auto-negotiation complete 100 = Polarity reversed 101 = Jabber detected 110 = Interrupt pending 111 = Reserved These three bits select which status information is available on the RxData(0) bit of the RMII bus. 000 = Link 001 = Speed 010 = Duplex 011 = Auto-negotiation complete 100 = Polarity reversed 101 = Jabber detected 110 = Interrupt pending 111 = Reserved 0 = Disable Out-of-Band signaling. 1 = Enable programmable RMII Out-of-Band signaling. When enabled, Register bits 6:1 specify which status bits are available on the RMII RxData data bus.
Note: Out-of-Band signaling is disabled when the Isolate mode is enabled by setting Register bit 0.10.
R/W
0x000
6:4
BIT1
R/W
000
3:1
BIT0
R/W
000
0
PROGRMII
R/W
0
1. R/W = Read/Write NOTE: The BGA15 package does not support RMII operation.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
215
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 1 of 2)
Bit Name Description Type5 Default
15:13 12
Reserved Reserved
Write as 0, ignore on Read Write as 0, ignore on Read. 00 = 3.3 ns 01 = 3.6 ns 10 = 3.9 ns 11 = 4.2 ns
NOTE: Values represent nominal load conditions.
R R/W
N/A 0
11:10
Per-Port Rise Time Control
R/W
LSHR1,2
9
AMDIX_EN
0 = Disable auto MDI/MDIX 1 = Enable auto MDI/MDIX 0 = MDI, transmit on pair A (TPFINn/TPFIPn) and receive on pair B (TPFONn/TPFOPn) 1 = MDIX transmit on pair B (TPFONn/TPFOPn) and receive on pair A (TPFINn/TPFIPn)
R/W
LSHR1,3
8
MDIX
NOTE: Manual MDI/MDIX selection (This bit is ignored when Register bit 27.9 = 1). NOTE: BGA15 does not support the MDIX hardware configuration.
R/W
LSHR1,4
7
Analog Loopback
0 = Disable analog loopback 1 = Enable analog loopback (twisted-pair transmit outputs are active)
NOTE: In fiber mode, SD for the port must be asserted. DTE Discovery Process Enable.
R/W
0
6
Dis_EN
0 = Disable DTE discovery process 1 = Enable DTE discovery process Restart auto-negotiation after writing to this bit to ensure proper operation.
R/W
0
5
Reserved
Write as 0, ignore on Read.
Power Enable (Requires Auto-Negotiation Enable Register bit 0.12 = 1).
R/W
0
4
Power_EN
0 = Remote-Power DTE not discovered; process may not be complete. 1 = Potential Remote-Power DTE discovered; indication to turn on power over the cable.
R
0
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins. 3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin. 4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX hardware configuration. The BGA15 default = 0. 5. R/W = Read/Write, R = Read Only, LH = Latching High - cleared when read. 6.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 99. Trim Enable Register (Address 27, Hex 1B) (Sheet 2 of 2)
Bit Name Description Standard Link Partner Detected. Type5 Default
3
SLP_Det
0 = Standard link partner not discovered; process may not be complete. 1 = Standard link partner discovered; indication not to turn on power over the cable.
Note: This bit is only valid while link is down. Link Fail Inhibit Timer expiration indicator. Valid only when SLP_Det = 1.
R, LH
0
2
LFIT Expired
0 = Link Fail Inhibit Timer has not expired or standard link partner not discovered 1 = Link Fail Inhibit Timer expired with a standard link partner detected since last register read or link establishment Write as 0, ignore on Read.
R, LH
0
1:0
Reserved
R
00
1. LSHR = Default value is derived from a single device input pin state or a group of device input pin states as the pin(s) are latched at startup or hardware reset. 2. Default values for Register bits 27.11:10 are determined by the TxSLEW pins. 3. Default value for Register bit 27.9 is determined by the AMDIX_EN pin. 4. Default value for Register bit 27.8 is determined by the MDIX pin. BGA15 does not support the MDIX hardware configuration. The BGA15 default = 0. 5. R/W = Read/Write, R = Read Only, LH = Latching High - cleared when read. 6.
Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 1 of 2)
Bit Name Description Type1 Default2
15:14
Reserved
Write as 01, ignore on read 000 = Do not perform cable fault test (Default) 101 = Perform long cable fault test only 110 = Perform short cable fault test only
R/W
01
13:11
Start-Test
Once Register bit 29.9 is set, the Start-Test bits will clear when read. Any other combination of the Register bit settings are reserved and should not be used.
R/W LH
000
10
CD_EN
0 = Normal operation 1 = Enable cable diagnostic tests. Forces link to drop.
R/W
0
1. R/W = Read/Write, R = Read only, LH = Latching High, cleared when read 2. Recommended default value.
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
217
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 100. Cable Diagnostics Register (Address 29, Hex 1D) (Sheet 2 of 2)
Bit Name Description Type1 Default2
9
Test_Done
0 = Testing is still in progress 1 = Testing is complete The Line Fault Counter and Fault_Type bits are valid. 0 = Open condition has been detected 1 = Short Condition has been detected "FF" if no line fault is found, or Distance to fault, approximately 1 m * counter value (refer to Section 4.13, "Cable Diagnostics Overview" on page 160 for details). (Valid only when Test_Done bit is set.)
R LH R LH
0
8
Fault_Type
0
7:0
Line Fault Counter
R LH
0x00
1. R/W = Read/Write, R = Read only, LH = Latching High, cleared when read 2. Recommended default value.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Table 101. Intel(R) LXT9785/LXT9785E Register Bit Map (Sheet 1 of 2)
Bit Fields Addr B14 Control Register (Address 0)
Loopback Speed Select Isolate COL Test Reserved A/N Enable Power Down Re-start A/N Duplex Mode Speed Select
Reg Title B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Datasheet
0 Status Register (Address 1)
100BaseX FullDuplex 100Base-X Half-Duplex 100Base-T2 Half-Duplex Reserved A/N Ability Extended Status A/N Complete Remote Fault 10 Mbps FullDuplex 10 Mbps HalfDuplex 100BaseT2 FullDuplex MF Preamble Suppress Link Status Jabber Detect Extended Capability
B15
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Control
Reset
Status PHY ID Registers (Address 2 and 3)
14 13 12 11 10 9 8 7 6 5 4 3 2
100Base-T4
1
PHY ID 1
PHY ID No MFR Model No
15
1
0
2
MFR Rev No Model Variant
PHY ID2 Auto-Negotiation Advertisement Register (Address 4)
Reserved Remote Fault Reserved Asymm Pause Pause 100Base-T4 100BaseTX FullDuplex 100BaseTX 10Base-T Full-Duplex 10Base-T
3
A/N Advertise
Next Page
IEEE Selector Field
4
Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Ack Remote Fault Reserved Asymm Pause Pause 100Base-T4 100BaseTX FullDuplex 100BaseTX 10Base-T Full-Duplex 10Base-T IEEE Selector Field
A/N Link Ability
Next Page
5
Auto-Negotiation Expansion Register (Address 6)
Reserved Base Page Parallel Detect Fault Link Partner Next Page Able Next Page Able Page Received Link Partner A/N Able
A/N Expansion
6
Auto-Negotiation Next Page Transmit Register (Address 7)
Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field
A/N Next Page Txmit
Next Page
7
Auto-Negotiation Link Partner Next Page Ability Register (Address 8)
Ack Message Page Ack 2 Toggle Message / Unformatted Code Field
A/N Link Next Page
Next Page
8 Port Configuration Register (Address 16)
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
219
Table 101. Intel(R) LXT9785/LXT9785E Register Bit Map (Sheet 2 of 2)
Bit Fields Addr B14
Link Disable Reserved Reserved PRE_EN Reserved Reserved Reserved Txmit Disable Bypass Scrambler (100BASETX) Jabber (10T) Far End Fault Enable SQE (10T) TP Loopback (10T) Fiber Select Bypass 4B/5B (100BASE -TX)
220
B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 16 Quick Status Register (Address 17)
10/100 Mode Link Duplex Mode Auto-Neg FIFO Error Polarity Pause Error Reserved Transmit Status Receiver Status Collision Status Auto-Neg Complete Reserved Reserved
Reg Title
B15
Port Config
Reserved
Quick Status Interrupt Enable Register (Address 18)
Reserved Counter Mask Speed Mask Link Mask Auto-Neg Mask Duplex Mask Isolate Mask Reserved
Reserved
17
Interrupt Enable Interrupt Status Register (Address 19)
Reserved RxER Counter Full Auto-Neg Done Speed Change Duplex Change Link Change Isolate Change
Interrupt Enable
Test Interrupt
18
Interrupt Status LED Configuration Register (Address 20)
LED1 LED2 LED3
MD Interrupt
Reserved
Reserved
19
LED Config Receive Error Count Register (Address 21)
Receive Error Count
LED Freq
Pulse Stretch
Reserved
20
Rcv Error Count
21
Programmable RMII Out-of-Band Signaling Register (Register 25)
Reserved Bit 1 Bit 0 Program RMII
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
RMII OOB Signaling
25
Trim Enable Register (Address 27)
Per Port Rise Time Control Reserved AMDIX_EN MDIX Analog Loopback Dis_EN Loop Back Speed Up Enable Power_EN SLP_Det LFIT Expired Reserved
Trim Enable
27
Cable Diagnostics Register (Address 29)
Start-Test
CD_EN Test-Done Fault_ Type Line Fault Counter
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
Datasheet
Cable Diagnostics
Reserved
29
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
8.0
Package Specifications
Figure 64. Intel(R) LXT9785/LXT9785E 208-Pin PQFP Plastic Package Specification 208-Pin Plastic Quad Flat Package
* Part Number LXT9785HC, LXT9785EHC,
LXT9785HE
* Commercial Temperature Range (0C to 70C) * Extended Temperature Range (-40C to +85C)
D D1
Millimeters Dim Min
e
Max
A A1 A2
e
0.25 3.20 0.17 30.30 27.70 30.30 27.70
4.10 3.60 0.27 30.90 28.30 30.90 28.30 .50 BASIC
E1
E /2
b D D1 E E1 e L
2 L1 A A2 A1 L b 3
0.50 1.30 REF 0 5 5
0.75
L1 q 2 3
7 16 16
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
221
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 65. Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Top/Side View (LXT9785BC)
D Pin A1 corner D1
Pin A1 I.D.
14.70 REF
E1 E
14.70 REF
45 Chamfer (4 places) A2 c A1 A
Top View
30
Side View
Seating Plane 241_pkg1.vsd
222
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 66. Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Package Specs - Bottom View (LXT9785BC)
Pin A1 corner 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B b C D E F e G H J K L M N P R T J e U
l
241 BGA Bottom View
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
223
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Intel(R) LXT9785/LXT9785E 241-Ball BGA23 Package Dimensions
Symbol Min Nominal Max Units Note
A A1 A2 D D1 E E1 e I J M b c e
2.19 0.50 1.12 22.90 19.30 22.90 19.30
2.38 0.60 1.17 23.00 19.50 23.00 19.50
2.57 0.70 1.22 23.10 19.70 23.10 19.70
mm mm mm mm mm mm mm mm mm mm mm
1.27 (solder ball pitch) 1.34 REF. 1.34 REF. 17 x 17 Matrix 0.60 0.52 0.75 0.56 1.27 0.90 0.60
mm mm mm
All dimensions and tolerances conform to ANSI Y14.5-1982. Dimension is measured at maximum solder ball diameter parallel to primary datum (-C-). Primary datum (-C-) and seating plane are defined by the spherical crowns of the solder balls.
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Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 67. Intel(R) LXT9785MBC 196-Ball BGA15 Package Specs - Top/Side View (LXT9785MBC)
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
225
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Table 102. Intel(R) LXT9785MBC 196-Ball BGA15 Package Dimensions
Symbol Min Nominal Max Units Note
A A1 A2 D D1 E E1 e I J M b c e
1.62 0.30 0.80 14.90 12.80 14.90 12.80 1.00 (solder ball pitch) 1.00 REF. 1.00 REF. 14 x 14 Matrix 0.40 0.52
1.81 0.40 0.85 15.00 13.00 15.00 13.00
2.00 0.50 0.90 15.10 13.20 15.10 13.20
mm mm mm mm mm mm mm mm mm mm mm
0.50 0.56 1.00
0.60 0.60
mm mm mm
NOTE: All dimensions and tolerances conform to ANSI Y14.5-1982.Dimension is measured at maximum solder ball diameter parallel to primary datum (-C-). Primary datum (-C-) and seating plane are defined by the spherical crowns of the solder balls.
226
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
9.0
Ordering Information
Table 103. Product Information
Number Revision Qualification Tray MM Tape & Reel MM
HBLXT9785HC.D0 853353 HBLXT9785HC.D0 853355 FWLXT9785BC.D0 853308 FWLXT9785BC.D0 853312 HBLXT9785EHC.D0 853334 HBLXT9785EHC.D0 853335 FWLXT9785EBC.D0 853300 FWLXT9785EBC.D0 853304 HBLXT9785HE.D0 853357 HBLXT9785HE.D0 853363 GDLXT9785MBC.D0 GDLXT9785MBC.D0
D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0
S S S S S S S S S S Q Q
853353 853355 853308 853312 853334 853335 853300 853304 853357 853363 TBD TBD
Tray Tape & reel Tray Tape & reel Tray Tape & reel Tray Tape & reel Tray Tape & reel TBD TBD
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003
227
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
Figure 68. Ordering Information - Sample
FW LXT 9785 B C D0 S E001 Build Format E000 = Tray E001 = Tape and reel Qualification = Pre-production material Q = Production material S
Product Revision = 2 Alphanumeric characters xn Temperature Range = Ambient (0 - 55 C) A = Commercial (0 - 70 C) C = Extended (-40 - +85 C) E Internal Package Designator = LQFP L = PLCC P = DIP N = PQFP Q = QFP with heat spreader H = TQFP T = BGA B = CBGA C = TBGA E = HSBGA (BGA with heat slug) K xxxx = 3-5 Digit Alphanumeric Product Code
IXA Product Prefix = PHY layer device LXT = Switching engine IXE = Formatting device (MAC) IXF = Network processor IXP Intel Package Designator DJ = LQFP FA = TQFP FL = PBGA (<1.0 mm pitch) FW = PBGA (1.27 mm pitch) HB = QFP with heat spreader HD = QFP with heat slug HF = CBGA HG = SOIC S = QFP GC = TBGA N = PLCC
228
Datasheet
Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003

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